WIP: riscv64: Use the zero register directly

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -5,6 +5,8 @@
  (Nop0)
  (Nop4)
 
+ (Zero (rd WritableReg))
+
  ;; load immediate
  (Lui
  (rd WritableReg)
@@ -1729,12 +1731,18 @@
 (decl imm (Type u64) Reg)
 
 ;; Refs get loaded as integers.
-(rule 5 (imm $R32 c) (imm $I32 c))
-(rule 5 (imm $R64 c) (imm $I64 c))
+(rule 6 (imm $R32 c) (imm $I32 c))
+(rule 6 (imm $R64 c) (imm $I64 c))
 
 ;; Floats get loaded as integers and then moved into an F register.
-(rule 5 (imm $F32 c) (gen_bitcast (imm $I32 c) $I32 $F32))
-(rule 5 (imm $F64 c) (gen_bitcast (imm $I64 c) $I64 $F64))
+(rule 6 (imm $F32 c) (gen_bitcast (imm $I32 c) $I32 $F32))
+(rule 6 (imm $F64 c) (gen_bitcast (imm $I64 c) $I64 $F64))
+
+;; Try to match just an imm12
+(rule 5 (imm (ty_int ty) 0)
+ (let ((dst WritableReg (temp_writable_xreg))
+ (_ Unit (emit (MInst.Zero dst))))
+ dst))
 
 ;; Try to match just an imm12
 (rule 4 (imm (ty_int ty) c)

cranelift/codegen/src/isa/riscv64/inst/emit.rs

@@ -321,6 +321,7 @@ impl Inst {
  match self {
  Inst::Nop0
  | Inst::Nop4
+ | Inst::Zero { .. }
  | Inst::BrTable { .. }
  | Inst::Auipc { .. }
  | Inst::Lui { .. }
@@ -1025,6 +1026,7 @@ impl Inst {
  };
  x.emit(&[], sink, emit_info, state)
  }
+ &Inst::Zero { rd: _ } => {} // this is a pseudo-instruction.
  &Inst::RawData { ref data } => {
  // Right now we only put a u32 or u64 in this instruction.
  // It is not very long, no need to check if need `emit_island`.
@@ -3341,6 +3343,9 @@ impl Inst {
  match self {
  Inst::Nop0 => self,
  Inst::Nop4 => self,
+ Inst::Zero { rd } => Inst::Zero {
+ rd: allocs.next_writable(rd),
+ },
  Inst::RawData { .. } => self,
  Inst::Lui { rd, imm } => Inst::Lui {
  rd: allocs.next_writable(rd),

cranelift/codegen/src/isa/riscv64/inst/mod.rs

@@ -357,6 +357,9 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
  match inst {
  &Inst::Nop0 => {}
  &Inst::Nop4 => {}
+ &Inst::Zero { rd } => {
+ collector.reg_fixed_def(rd, zero_reg());
+ }
  &Inst::BrTable {
  index, tmp1, tmp2, ..
  } => {
@@ -1076,6 +1079,9 @@ impl Inst {
  &Inst::Nop4 => {
  format!("##fixed 4-size nop")
  }
+ &Inst::Zero { rd } => {
+ format!("zero {}", format_reg(rd.to_reg(), allocs))
+ }
  &Inst::StackProbeLoop {
  guard_size,
  probe_count,

cranelift/codegen/src/machinst/reg.rs

@@ -435,10 +435,10 @@ impl<'a, F: Fn(VReg) -> VReg> OperandCollector<'a, F> {
  pub fn reg_fixed_def(&mut self, reg: Writable<Reg>, rreg: Reg) {
  debug_assert!(reg.to_reg().is_virtual());
  let rreg = rreg.to_real_reg().expect("fixed reg is not a RealReg");
- debug_assert!(
- self.is_allocatable_preg(rreg.into()),
- "{rreg:?} is not allocatable"
- );
+ // debug_assert!(
+ //  self.is_allocatable_preg(rreg.into()),
+ //  "{rreg:?} is not allocatable"
+ // );
  self.add_operand(Operand::reg_fixed_def(reg.to_reg().into(), rreg.into()));
  }
 

cranelift/filetests/filetests/isa/riscv64/bitops-float.clif

@@ -21,53 +21,63 @@ block1(v4: f32):
 
 ; VCode:
 ; block0:
-; li a0,0
-; li a1,0
-; fmv.w.x fa3,a1
-; fmv.x.w a1,fa3
-; not a2,a1
+; zero zero
+; mv a4,zero
+; zero zero
+; fmv.w.x fa3,zero
+; fmv.x.w a0,fa3
+; not a2,a0
 ; fmv.w.x fa4,a2
 ; fmv.x.w a5,fa4
 ; fmv.x.w a1,fa4
 ; or a3,a5,a1
 ; fmv.w.x fa4,a3
-; br_table a0,[MachLabel(1),MachLabel(2)]##tmp1=a1,tmp2=a2
+; mv zero,a4
+; br_table zero,[MachLabel(1),MachLabel(2)]##tmp1=a1,tmp2=a2
 ; block1:
+; mv a4,zero
+; mv a0,a4
 ; j label3
 ; block2:
+; mv a4,zero
 ; fmv.d fa4,fa3
+; mv a0,a4
 ; j label3
 ; block3:
 ; ret
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-; mv a0, zero
-; mv a1, zero
-; fmv.w.x fa3, a1
-; fmv.x.w a1, fa3
-; not a2, a1
+; mv a4, zero
+; fmv.w.x fa3, zero
+; fmv.x.w a0, fa3
+; not a2, a0
 ; fmv.w.x fa4, a2
 ; fmv.x.w a5, fa4
 ; fmv.x.w a1, fa4
 ; or a3, a5, a1
 ; fmv.w.x fa4, a3
-; slli t6, a0, 0x20
+; mv zero, a4
+; slli t6, zero, 0x20
 ; srli t6, t6, 0x20
 ; addi a2, zero, 1
 ; bltu t6, a2, 0xc
 ; auipc a2, 0
-; jalr zero, a2, 0x28
+; jalr zero, a2, 0x20
 ; auipc a1, 0
 ; slli a2, t6, 3
 ; add a1, a1, a2
 ; jalr zero, a1, 0x10
 ; auipc a2, 0
-; jalr zero, a2, 0xc
+; jalr zero, a2, 0x14
 ; block1: ; offset 0x58
-; j 8
-; block2: ; offset 0x5c
+; mv a4, zero
+; mv a0, a4
+; j 0x10
+; block2: ; offset 0x64
+; mv a4, zero
 ; fmv.d fa4, fa3
-; block3: ; offset 0x60
+; mv a0, a4
+; block3: ; offset 0x70
 ; ret
 

cranelift/filetests/filetests/isa/riscv64/bitops.clif

@@ -410,7 +410,8 @@ block0(v0: i128):
 ; clz a3,a0##ty=i64 tmp=a4 step=a2
 ; select a0,a3,zero##condition=(a1 eq zero)
 ; add a0,a5,a0
-; li a1,0
+; zero zero
+; mv a1,zero
 ; ret
 ;
 ; Disassembled:
@@ -612,7 +613,8 @@ block0(v0: i128):
 ; select a2,a0,zero##condition=(a3 eq zero)
 ; add a3,a1,a2
 ; addi a0,a3,-1
-; li a1,0
+; zero zero
+; mv a1,zero
 ; ret
 ;
 ; Disassembled:
@@ -778,7 +780,8 @@ block0(v0: i128):
 ; ctz a3,a0##ty=i64 tmp=a1 step=a2
 ; select a5,a5,zero##condition=(a0 eq zero)
 ; add a0,a3,a5
-; li a1,0
+; zero zero
+; mv a1,zero
 ; ret
 ;
 ; Disassembled:
@@ -820,7 +823,8 @@ block0(v0: i128):
 ; popcnt a5,a0##ty=i64 tmp=a3 step=a4
 ; popcnt a3,a1##ty=i64 tmp=a4 step=a2
 ; add a0,a5,a3
-; li a1,0
+; zero zero
+; mv a1,zero
 ; ret
 ;
 ; Disassembled:

cranelift/filetests/filetests/isa/riscv64/brif.clif

@@ -21,7 +21,8 @@ block2:
 ; andi a4,a0,255
 ; bne a4,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -57,7 +58,8 @@ block2:
 ; srai a0,a4,48
 ; bne a0,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -93,7 +95,8 @@ block2:
 ; sext.w a4,a0
 ; bne a4,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -127,7 +130,8 @@ block2:
 ; block0:
 ; bne a0,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -161,7 +165,8 @@ block2:
 ; or a5,a0,a1
 ; bne a5,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -198,7 +203,8 @@ block2:
 ; andi a1,a1,255
 ; beq a5,a1,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -240,7 +246,8 @@ block2:
 ; srli a5,a3,48
 ; bne a1,a5,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -282,7 +289,8 @@ block2:
 ; sext.w a1,a1
 ; blt a5,a1,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -318,7 +326,8 @@ block2:
 ; block0:
 ; bgeu a0,a1,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -353,7 +362,8 @@ block2:
 ; sgt a1,[a0,a1],[a2,a3]##ty=i128
 ; bne a1,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -394,7 +404,8 @@ block2:
 ; flt.s a5,fa0,fa1
 ; bne a5,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1
@@ -430,7 +441,8 @@ block2:
 ; flt.d a5,fa0,fa1
 ; beq a5,zero,taken(label2),not_taken(label1)
 ; block1:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; ret
 ; block2:
 ; li a0,1

cranelift/filetests/filetests/isa/riscv64/call.clif

@@ -800,7 +800,8 @@ block0:
 
 ; VCode:
 ; block0:
-; li a0,0
+; zero zero
+; mv a0,zero
 ; li a1,1
 ; ret
 ;
@@ -857,3 +858,47 @@ block0(v0: i16):
 ; addi sp, sp, 0x10
 ; ret
 
+function %call_zero_argument() -> i16 {
+ sig0 = (i16) -> i16
+ fn0 = u0:0 sig0
+
+block0:
+ v0 = iconst.i16 0
+ v1 = call fn0(v0)
+ return v1
+}
+
+; VCode:
+; add sp,-16
+; sd ra,8(sp)
+; sd fp,0(sp)
+; mv fp,sp
+; block0:
+; zero zero
+; mv a0,zero
+; load_sym a2,userextname0+0
+; callind a2
+; ld ra,8(sp)
+; ld fp,0(sp)
+; add sp,+16
+; ret
+;
+; Disassembled:
+; block0: ; offset 0x0
+; addi sp, sp, -0x10
+; sd ra, 8(sp)
+; sd s0, 0(sp)
+; mv s0, sp
+; block1: ; offset 0x10
+; mv a0, zero
+; auipc a2, 0
+; ld a2, 0xc(a2)
+; j 0xc
+; .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 u0:0 0
+; .byte 0x00, 0x00, 0x00, 0x00
+; jalr a2
+; ld ra, 8(sp)
+; ld s0, 0(sp)
+; addi sp, sp, 0x10
+; ret
+