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riscv64: Add support for load+extend patterns #8765

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merged 2 commits into from
Jun 11, 2024

Commits on Jun 10, 2024

  1. riscv64: Add support for load+extend patterns

    RISC-V doesen't have sinkable loads per se, but the regular load
    instructions support sign / zero extending the loaded values.
    
    We model those here as a sinkable load on the extend instruction.
    afonso360 committed Jun 10, 2024
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Commits on Jun 11, 2024

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