Add parens around guard exprs (#1858)

calyxir · Feb 16, 2024 · c918bb3 · c918bb3
1 parent d9061fd
commit c918bb3
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Showing 10 changed files with 22 additions and 22 deletions.
diff --git a/calyx-py/calyx/py_ast.py b/calyx-py/calyx/py_ast.py
@@ -276,7 +276,7 @@ class And(GuardExpr):
  right: GuardExpr
 
  def doc(self) -> str:
- return f"{self.left.doc()} & {self.right.doc()}"
+ return f"({self.left.doc()} & {self.right.doc()})"
 
 
 @dataclass
@@ -285,7 +285,7 @@ class Or(GuardExpr):
  right: GuardExpr
 
  def doc(self) -> str:
- return f"{self.left.doc()} | {self.right.doc()}"
+ return f"({self.left.doc()} | {self.right.doc()})"
 
 
 @dataclass

diff --git a/calyx-py/test/builder_example.expect b/calyx-py/test/builder_example.expect
@@ -13,7 +13,7 @@ component main(in: 32) -> (out: 32) {
  rhs.write_en = 1'd1;
  lhs.in = 32'd1;
  rhs.in = 32'd41;
- update_operands[done] = lhs.done & rhs.done ? 1'd1;
+ update_operands[done] = (lhs.done & rhs.done) ? 1'd1;
  }
  group compute_sum {
  add.left = lhs.out;

diff --git a/calyx-py/test/example.expect b/calyx-py/test/example.expect
@@ -13,7 +13,7 @@ component main() -> () {
  rhs.in = 32'd41;
  lhs.write_en = 1'd1;
  rhs.write_en = 1'd1;
- update_operands[done] = lhs.done & rhs.done ? 1'd1;
+ update_operands[done] = (lhs.done & rhs.done) ? 1'd1;
  }
  group compute_sum {
  add.left = lhs.out;

diff --git a/tests/frontend/exp/degree-2-unsigned.expect b/tests/frontend/exp/degree-2-unsigned.expect
@@ -39,7 +39,7 @@ component exp(x: 32) -> (out: 32) {
  frac_x.write_en = 1'd1;
  int_x.in = rsh.out;
  frac_x.in = and1.out;
- split_bits[done] = int_x.done & frac_x.done ? 1'd1;
+ split_bits[done] = (int_x.done & frac_x.done) ? 1'd1;
  }
  group consume_pow2<"static"=1> {
  p2.write_en = 1'd1;
@@ -114,7 +114,7 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
  pow.write_en = 1'd1;
  count.in = 32'd0;
  count.write_en = 1'd1;
- init[done] = pow.done & count.done ? 1'd1;
+ init[done] = (pow.done & count.done) ? 1'd1;
  }
  group execute_mul {
  mul.left = base;

diff --git a/tests/frontend/exp/degree-4-signed.expect b/tests/frontend/exp/degree-4-signed.expect
@@ -56,7 +56,7 @@ component exp(x: 16) -> (out: 16) {
  frac_x.write_en = 1'd1;
  int_x.in = rsh.out;
  frac_x.in = and1.out;
- split_bits[done] = int_x.done & frac_x.done ? 1'd1;
+ split_bits[done] = (int_x.done & frac_x.done) ? 1'd1;
  }
  group negate {
  mult_pipe1.left = exponent_value.out;
@@ -207,7 +207,7 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
  pow.write_en = 1'd1;
  count.in = 16'd0;
  count.write_en = 1'd1;
- init[done] = pow.done & count.done ? 1'd1;
+ init[done] = (pow.done & count.done) ? 1'd1;
  }
  group execute_mul {
  mul.left = base;

diff --git a/tests/frontend/exp/degree-4-unsigned.expect b/tests/frontend/exp/degree-4-unsigned.expect
@@ -53,7 +53,7 @@ component exp(x: 16) -> (out: 16) {
  frac_x.write_en = 1'd1;
  int_x.in = rsh.out;
  frac_x.in = and1.out;
- split_bits[done] = int_x.done & frac_x.done ? 1'd1;
+ split_bits[done] = (int_x.done & frac_x.done) ? 1'd1;
  }
  group consume_pow2<"static"=1> {
  p2.write_en = 1'd1;
@@ -178,7 +178,7 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
  pow.write_en = 1'd1;
  count.in = 16'd0;
  count.write_en = 1'd1;
- init[done] = pow.done & count.done ? 1'd1;
+ init[done] = (pow.done & count.done) ? 1'd1;
  }
  group execute_mul {
  mul.left = base;

diff --git a/tests/frontend/ntt-pipeline/ntt-4-reduced-2.expect b/tests/frontend/ntt-pipeline/ntt-4-reduced-2.expect
@@ -45,7 +45,7 @@ component main() -> () {
  r0.in = a.read_data;
  phi0.write_en = 1'd1;
  phi0.in = phis.read_data;
- preamble_0[done] = r0.done & phi0.done ? 1'd1;
+ preamble_0[done] = (r0.done & phi0.done) ? 1'd1;
  }
  group preamble_1 {
  a.addr0 = 3'd1;
@@ -54,7 +54,7 @@ component main() -> () {
  r1.in = a.read_data;
  phi1.write_en = 1'd1;
  phi1.in = phis.read_data;
- preamble_1[done] = r1.done & phi1.done ? 1'd1;
+ preamble_1[done] = (r1.done & phi1.done) ? 1'd1;
  }
  group preamble_2 {
  a.addr0 = 3'd2;
@@ -63,7 +63,7 @@ component main() -> () {
  r2.in = a.read_data;
  phi2.write_en = 1'd1;
  phi2.in = phis.read_data;
- preamble_2[done] = r2.done & phi2.done ? 1'd1;
+ preamble_2[done] = (r2.done & phi2.done) ? 1'd1;
  }
  group preamble_3 {
  a.addr0 = 3'd3;
@@ -72,7 +72,7 @@ component main() -> () {
  r3.in = a.read_data;
  phi3.write_en = 1'd1;
  phi3.in = phis.read_data;
- preamble_3[done] = r3.done & phi3.done ? 1'd1;
+ preamble_3[done] = (r3.done & phi3.done) ? 1'd1;
  }
  group precursor_0 {
  r0.in = A0.out;

diff --git a/tests/frontend/ntt-pipeline/ntt-4.expect b/tests/frontend/ntt-pipeline/ntt-4.expect
@@ -45,7 +45,7 @@ component main() -> () {
  r0.in = a.read_data;
  phi0.write_en = 1'd1;
  phi0.in = phis.read_data;
- preamble_0[done] = r0.done & phi0.done ? 1'd1;
+ preamble_0[done] = (r0.done & phi0.done) ? 1'd1;
  }
  group preamble_1 {
  a.addr0 = 3'd1;
@@ -54,7 +54,7 @@ component main() -> () {
  r1.in = a.read_data;
  phi1.write_en = 1'd1;
  phi1.in = phis.read_data;
- preamble_1[done] = r1.done & phi1.done ? 1'd1;
+ preamble_1[done] = (r1.done & phi1.done) ? 1'd1;
  }
  group preamble_2 {
  a.addr0 = 3'd2;
@@ -63,7 +63,7 @@ component main() -> () {
  r2.in = a.read_data;
  phi2.write_en = 1'd1;
  phi2.in = phis.read_data;
- preamble_2[done] = r2.done & phi2.done ? 1'd1;
+ preamble_2[done] = (r2.done & phi2.done) ? 1'd1;
  }
  group preamble_3 {
  a.addr0 = 3'd3;
@@ -72,7 +72,7 @@ component main() -> () {
  r3.in = a.read_data;
  phi3.write_en = 1'd1;
  phi3.in = phis.read_data;
- preamble_3[done] = r3.done & phi3.done ? 1'd1;
+ preamble_3[done] = (r3.done & phi3.done) ? 1'd1;
  }
  group precursor_0 {
  r0.in = A0.out;

diff --git a/tests/frontend/relay/softmax.expect b/tests/frontend/relay/softmax.expect
@@ -379,7 +379,7 @@ component exp(x: 32) -> (out: 32) {
  frac_x.write_en = 1'd1;
  int_x.in = rsh.out;
  frac_x.in = and1.out;
- split_bits[done] = int_x.done & frac_x.done ? 1'd1;
+ split_bits[done] = (int_x.done & frac_x.done) ? 1'd1;
  }
  group negate {
  mult_pipe1.left = exponent_value.out;
@@ -628,7 +628,7 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
  pow.write_en = 1'd1;
  count.in = 32'd0;
  count.write_en = 1'd1;
- init[done] = pow.done & count.done ? 1'd1;
+ init[done] = (pow.done & count.done) ? 1'd1;
  }
  group execute_mul {
  mul.left = base;

diff --git a/tests/frontend/systolic/array-1.expect b/tests/frontend/systolic/array-1.expect
@@ -148,7 +148,7 @@ component default_post_op(out_mem_0_done: 1, r0_valid: 1, r0_value: 32, r0_idx:
  }
  static<1> group write_done_cond {
  delay_reg.in = 1'd1;
- delay_reg.write_en = r0_valid & r0_idx == 1'd0 ? 1'd1;
+ delay_reg.write_en = (r0_valid & r0_idx == 1'd0) ? 1'd1;
  computation_done = delay_reg.done ? 1'd1;
  }
  }
@@ -184,7 +184,7 @@ component main() -> () {
  post_op_component.r0_idx = systolic_array_component.r0_idx;
  systolic_done.write_en = systolic_array_component.done ? 1'd1;
  systolic_done.in = systolic_array_component.done ? 1'd1;
- systolic_done_wire.in = systolic_array_component.done | systolic_done.out ? 1'd1;
+ systolic_done_wire.in = (systolic_array_component.done | systolic_done.out) ? 1'd1;
  systolic_array_component.go = !systolic_done_wire.out ? 1'd1;
  systolic_array_component.depth = 32'd3;
  post_op_component.go = 1'd1;