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add tests for parser error messages. Fixes #208
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,9 @@ | ||
---CODE--- | ||
1 | ||
---STDERR--- | ||
Error: FuTIL Parser: --> 3:5 | ||
| | ||
3 | r = prim std_reg(32)␊ | ||
| ^--- | ||
| | ||
= expected cell |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
component main() -> () { | ||
cells { | ||
r = prim std_reg(32) | ||
} | ||
wires { } | ||
control { } | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,9 @@ | ||
---CODE--- | ||
1 | ||
---STDERR--- | ||
Error: FuTIL Parser: --> 4:12 | ||
| | ||
4 | r.in = 1;␊ | ||
| ^ | ||
| | ||
= Expected number with bitwidth (like 32'd10). |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
component main() -> () { | ||
cells { } | ||
wires { | ||
r.in = 1; | ||
} | ||
control { } | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,11 @@ | ||
---CODE--- | ||
1 | ||
---STDERR--- | ||
Error: FuTIL Parser: --> 5:27 | ||
| | ||
5 | while r.out with cond {␊ | ||
| ... | ||
9 | }␊ | ||
| ^---------------------^ | ||
| | ||
= Sequence of control statements should be enclosed in `seq` or `par`. |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,11 @@ | ||
component main() -> () { | ||
cells { } | ||
wires { } | ||
control { | ||
while r.out with cond { | ||
upd0; | ||
upd1; | ||
upd2; | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,9 @@ | ||
---CODE--- | ||
1 | ||
---STDERR--- | ||
Error: FuTIL Parser: --> 4:16 | ||
| | ||
4 | r.in = 10'b22;␊ | ||
| ^^ | ||
| | ||
= Expected binary number |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
component main() -> () { | ||
cells { } | ||
wires { | ||
r.in = 10'b22; | ||
} | ||
control { } | ||
} |