recoded format to standard format primitive and its test case

primitives/float/HardFloat_consts.vi

@@ -0,0 +1,61 @@
+`ifndef __HARDFLOAT_CONSTS_VI__
+`define __HARDFLOAT_CONSTS_VI__
+
+/*============================================================================
+
+This Verilog include file is part of the Berkeley HardFloat IEEE Floating-
+Point Arithmetic Package, Release 1, by John R. Hauser.
+
+Copyright 2019 The Regents of the University of California.  All rights
+reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+`define round_near_even   3'b000
+`define round_minMag      3'b001
+`define round_min         3'b010
+`define round_max         3'b011
+`define round_near_maxMag 3'b100
+`define round_odd         3'b110
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+`define floatControlWidth 1
+`define flControl_tininessBeforeRounding 1'b0
+`define flControl_tininessAfterRounding  1'b1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+`define flRoundOpt_sigMSBitAlwaysZero  1
+`define flRoundOpt_subnormsAlwaysExact 2
+`define flRoundOpt_neverUnderflows     4
+`define flRoundOpt_neverOverflows      8
+
+`endif /* __HARDFLOAT_CONSTS_VI__ */

primitives/float/HardFloat_specialize.vi

@@ -0,0 +1,55 @@
+`ifndef __HARDFLOAT_SPECIALIZE_VI__
+`define __HARDFLOAT_SPECIALIZE_VI__
+
+/*============================================================================
+
+This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
+Arithmetic Package, Release 1, by John R. Hauser.
+
+Copyright 2019 The Regents of the University of California.  All rights
+reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+module
+    iNFromException#(parameter width = 1) (
+        input signedOut,
+        input isNaN,
+        input sign,
+        output [(width - 1):0] out
+    );
+
+    wire maxInt = isNaN || !sign;
+    assign out = {signedOut ^ maxInt, {(width - 1){maxInt}}};
+
+endmodule
+
+`endif /* __HARDFLOAT_SPECIALIZE_VI__ */

primitives/float/RISCV/HardFloat_specialize.vi

@@ -0,0 +1,52 @@
+`ifndef __RISCV_HARDFLOAT_SPECIALIZE_VI__
+`define __RISCV_HARDFLOAT_SPECIALIZE_VI__
+
+/*============================================================================
+
+This Verilog include file is part of the Berkeley HardFloat IEEE Floating-
+Point Arithmetic Package, Release 1, by John R. Hauser.
+
+Copyright 2019 The Regents of the University of California.  All rights
+reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+`define flControl_default `flControl_tininessAfterRounding
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+//`define HardFloat_propagateNaNPayloads
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+`define HardFloat_signDefaultNaN 0
+`define HardFloat_fractDefaultNaN(sigWidth) {1'b1, {((sigWidth) - 2){1'b0}}}
+
+`endif /* __RISCV_HARDFLOAT_SPECIALIZE_VI__ */

primitives/float/recFNToFN.futil

@@ -0,0 +1,14 @@
+/// ======================================================================
+// Wrapper for HardFloat's recoded-format-to-standard module
+/// ======================================================================
+
+extern "recFNToFN.sv" {
+  // Convert from recoded floating-point to standard format
+  primitive recFNToFN[
+    expWidth, sigWidth, inputWidth, outputWidth
+  ](
+    in_: inputWidth
+  ) -> (
+    @stable out: outputWidth
+  );
+}

primitives/float/recFNToFN.sv

@@ -0,0 +1,86 @@
+`ifndef __HARDFLOAT_RECFNTOFN_V__
+`define __HARDFLOAT_RECFNTOFN_V__
+
+`include "primitives/float/HardFloat_rawFN.sv"
+
+/*============================================================================
+
+This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
+Arithmetic Package, Release 1, by John R. Hauser.
+
+Copyright 2019 The Regents of the University of California.  All rights
+reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/* ============= Added section to include some files ================== */
+// verilator lint_off MODDUP
+//`include "includeFile.v"
+// verilator lint_on MODDUP
+/* ============================================================== */
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+module
+  recFNToFN#(
+    parameter expWidth = 3, 
+    parameter sigWidth = 3,
+    parameter inputWidth = 7,
+    parameter outputWidth = 6
+) (
+    input [inputWidth-1:0] in_,
+    output [outputWidth-1:0] out
+  );
+`include "primitives/float/HardFloat_localFuncs.vi"
+
+  /*------------------------------------------------------------------------
+  *------------------------------------------------------------------------*/
+  localparam [expWidth:0] minNormExp = (1<<(expWidth - 1)) + 2;
+  localparam normDistWidth = clog2(sigWidth);
+  /*------------------------------------------------------------------------
+  *------------------------------------------------------------------------*/
+  wire isNaN, isInf, isZero, sign;
+  wire signed [(expWidth + 1):0] sExp;
+  wire [sigWidth:0] sig;
+  recFNToRawFN#(expWidth, sigWidth)
+      recFNToRawFN(in_, isNaN, isInf, isZero, sign, sExp, sig);
+  wire isSubnormal = (sExp < minNormExp);
+  /*------------------------------------------------------------------------
+  *------------------------------------------------------------------------*/
+  wire [(normDistWidth - 1):0] denormShiftDist = minNormExp - 1 - sExp;
+  wire [(expWidth - 1):0] expOut =
+      (isSubnormal ? 0 : sExp - minNormExp + 1)
+          | (isNaN || isInf ? {expWidth{1'b1}} : 0);
+  wire [(sigWidth - 2):0] fractOut =
+      isSubnormal ? (sig>>1)>>denormShiftDist : isInf ? 0 : sig;
+  assign out = {sign, expOut, fractOut};
+
+endmodule
+
+`endif /* __HARDFLOAT_RECFNTOFN_V__ */

tests/correctness/float/recFNToFN.expect

@@ -0,0 +1,8 @@
+{
+  "cycles": 1,
+  "memories": {
+    "mem": [
+      1132462096
+    ]
+  }
+}

tests/correctness/float/recFNToFN.futil

@@ -0,0 +1,26 @@
+import "primitives/core.futil";
+import "primitives/memories/comb.futil";
+import "primitives/float/recFNToFN.futil";
+
+component main(@go go: 1) -> (@done done: 1) {
+    cells {
+        @external mem = comb_mem_d1(32, 1, 1);
+
+        recFNToFN0 = recFNToFN(8, 24, 33, 32);
+    }
+
+    wires {
+        group standard_to_recoded {
+            recFNToFN0.in_ = 33'b010000100000000000000000000010000;
+
+            mem.addr0 = 1'b0;
+            mem.write_data = recFNToFN0.out;
+            mem.write_en = 1'd1;
+            standard_to_recoded[done] = mem.done;
+        }
+    }
+
+    control {
+        standard_to_recoded;
+    }
+}

tests/correctness/float/recFNToFN.futil.data

@@ -0,0 +1,10 @@
+{
+  "mem": {
+    "data": [0],
+    "format": {
+      "numeric_type": "bitnum",
+      "is_signed": false,
+      "width": 32
+    }
+  }
+}