Remove initialization of wires

[nathanielnrn]

No description provided.

[nathanielnrn]

Not sure where this takes places, do you maybe know off the top of your head @rachitnigam?

[rachitnigam]

If it's the verilog backend then here: https://github.com/cucapra/calyx/blob/master/src/backend/verilog.rs#L182

The --disable-init flag removes the initialize blocks. If you're talking about the axi backend then I'm not sure but it'll be axi.rs probably

[nathanielnrn]

Quick question that came up while working on this: Should

module std_wire #(
  parameter WIDTH = 32
) (
  input wire logic [WIDTH - 1:0] in,
  output logic [WIDTH - 1:0] out
);
  assign out = in;
endmodule

in port be a wire or just a logic (do people say this? Feels more natural to say reg.) @andrewb1999 changes has this as just a logic. See changed versus original

[rachitnigam]

Thats because we merged a change since then. You can look at the blame to see when that changed but I don't think you need to change anything here