Attributes everywhere

[rachitnigam]

Attribute annotations are currently limited to just groups. This proposal makes them available to cells, ports, and components. Attributes should become a general mechanism to attach extra information to various parts of the IL.

As a starting example, consider a type recovery pass that walks over cells and ports and tries to come up with signed or unsigned type for each:

component foo(@type("signed") inp1: 32) -> (@type("signed") out: 32) {
  cells {
    @type("unsigned") r = std_reg(32);
  }
}

Following the principle laid out in #270 ("everything that is solved for groups must be solved for components"), we can attach "static" information to a component and change the compilation of invoke (#273) to generate a faster FSM.

[sampsyo]

Nice. This is a cool idea. And I like the implicit proposal that we could use this for an optional "overlay" type system that actually represents data types.

[sgpthomas]

would be a useful debugging tool as well. for an analysis like live-range-analysis, it would be super useful to be able to annotate the things live at each group

[rachitnigam]

An annotation called "fsm" that the verilog backend can use to generate optimized case-based transition:

cells {
  @encoding("fsm") fsm = std_reg(32); // <- added during compilation
}

[cgyurgyik]

Another idea is following LLVM's opaque pointer approach, i.e., give types to reads/writes instead of the underlying memory. This is similar to what our binary operators currently do, and would ensure we don't have type clashing for the memory, which will likely be reinterpreted many different ways.

component foo(@type("signed") inp1: 32) -> (@type("signed") out: 32) {
  cells {
    r = std_reg(32);
  }
  wires {
    @type("unsigned") out = r.out; 
  }
}