Generalize sharing

[calebmkim]

Combined the minimize_regs pass and resource-sharing pass into 1 pass. Right now, they're both being done on the minimize_regs pass.

More detail:

So for minimize_regs I added 3 fields: shareable, state_shareable and cont_cells. I implemented the ConstructVisitor trait for MinimizeRegs, and the code I used to do that is almost the same as when ConstructVisitor was implemented in ResourceSharing. It takes in a context and looks for primitives and components marked with "share" and "state_share" attribute and adds it to the appropriate field.

We used the cont_cells field so that we could have a way of completely filtering out any cells used in any continuous assignments.

In the initialize method of MinimizeRegs we clone the "share" and "state_share" fields and pass them as arguments when we create the new LiveRangeAnalysis (line 91 of minimize_regs.rs) Here is what LiveRangeAnalysis does.

Let's look at the new function of LiveRangeAnalysis.

Its build_live_ranges functions basically the same as before. The only reason why we need the "state_share" is because, for a given cell, we want to check its cell type for membership in the state_share HashSet (edit: there is a helper method is_shareable_component to help do this) instead of checking if its type is std_reg . Even though these things are basically the same right now, it may be helpful in the future for components marked with the state_share attribute.

Then (looking at lines 294-310 of live_range_analysis.rs), it goes through each group and combinational group of the component, and looks for any use of a cell that has the "share" attribute. If it does, then it adds it as "live" in the group it is contained in. There is a helper function, add_shareable_ranges, to help factor out common code when doing this task.

Lmk if you need more detail: I can comment directly on the code if that's the case.

[rachitnigam]

Hey @calebmkim can you update the write up to discuss what code changes you made and how it works? It’s hard to understand complex changes like these without context

[calebmkim]

Just added context on writeup.

[rachitnigam]

This looks like a great start! I have a couple of code questions but I'd also like to get on a call and talk through the implementation before merging things.

[rachitnigam]

Ah, looks like some changes from the dominators stuff did creep in here. You can try fixing this by resetting your local to only have changes from the remote: git reset --hard origin generalize_sharing. This will make your local copy only have changes on this branch. Make sure you commit all of the dominators stuff on a different branch before doing this.

Next, you can write a commit that remove all the dominators stuff from this PR.

[rachitnigam]

One other thing I realized: we should ignore any cell that is marked as a ref from the sharing algorithm. You can use the is_reference method on cells to figure out if they are a ref cell.

[calebmkim]

@rachitnigam
In the process of writing test cases, I realized it won't be as easy as just slapping "state_share" onto things that we want to treat as registers.
The find_gen_kill_group() function has a special if block just for cases that "look like a register write", as detected by variable_like(). The main thing we might need to change in variable_like() is that it checks for write_en to be set to 1.
I will work to get this resolved for the next commit.

edit: I also handled the changed it to ignore ref_cells even though I forgot to say that in the commit message.

edit: For some reason it is failing some of the Dahila frontend tests. From what I can see just doing a quick look through, it looks like the errors are coming from the fact that my stuff is doing upd2[done] = C0_0_0.done instead of upd2[done] = C0_0_0.done ? 1'd1...

[rachitnigam]

The infer-static-timing pass has some generalized logic to detect if a group is using a component. Maybe that will be helpful?

[rachitnigam]

Just to expand on that comment a little bit more: the pass looks for the @go and @done annotations on ports to figure out when a component is being "run". The write_en port on a register is marked @go so it works out correctly

[sampsyo]

I don't know if this makes sense, but do we perhaps need a more flexible notion of what "looks like a write" to a given component? Like, maybe we want to consider that a component can be "used" for either reading or writing, just like a register, and both might involve enabling @go for the component. (Kinda recalls the evergreen "methods" idea…)

[calebmkim]

@rachitnigam I have updated the PR. The biggest change I have made is on variable_detection.rs in order to generalize it to state_share components instead of registers.

[rachitnigam]

Handles the first part of #1018!!