[Calyx-FIRRTL backend] Primitive Cells

[ayakayorihiro]

Note: I'm making this PR now so that I don't have any unfinished business left in 2023 😅 Please feel free to ignore until 2024!

I added support for cells that instantiate primitives! The approach involves (1) converting each unique primitive instantiation into a unique identifier (ex. std_add(32) → std_add_32), (2) creating an extmodule declaration at the beginning of the FIRRTL file for such identifiers, and (3) converting each cell instantiation to a corresponding inst ... statement in FIRRTL.
I also incorporated @EclecticGriffin 's feedback from the last PR into this one. Thanks again for the feedback!!

[EclecticGriffin]

Looks good to me! I only had very minor nits. Merge this whenever you're ready

[ayakayorihiro]

Thanks for the comments @EclecticGriffin ! Fixed and merged :)

[sampsyo]

Wow! This is AWESOME!!! Just calling out the important bit in the generated FIRRTL:

    extmodule std_add_32:
        defname = std_add
        parameter WIDTH = 32

Wahoo! This means, of course, is that "all we need" is an implementation of std_add to link against.

To summarize something @ayakayorihiro and I discussed synchronously, it probably makes sense to approach this in two steps:

1. Try compiling the FIRRTL to Verilog using official tooling (firtool, perhaps?) and link it against our existing Verilog implementations of the primitives. This gives us a scenic route to yet another a Verilog backend! 🤪 This at least lets us differentially test against the existing "real" Verilog backend in Calyx.
2. ESSENT does not support Verilog primitives (maybe that's obvious). So we need to generate primitive implementations in FIRRTL. The straightforward way to do this would be to write them by hand in Chisel and compile them to LoFIRRTL. That would effectively replace these extmodule declarations with proper modules with real implementations. The annoying part about this will be aligning the naming conventions so the two bits of FIRRTL (compiled from Calyx and compiled from Chisel) agree on what std_add_32 means.

[ayakayorihiro]

Thanks @sampsyo !! In my attempts to get Step 1 (from your above comment) going I realized there's a bug in the generated extmodule 😅 I didn't list out the inputs and outputs of the primitives in the extmodule declaration. I'm working on a fix right now, will make another smaller PR once that's done!