[Calyx-FIRRTL] Primitive cell bug fix #1838
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sampsyo
reviewed
Jan 5, 2024
calyx-backend/src/firrtl.rs
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| @@ -175,12 +152,17 @@ fn get_primitive_module_name(name: &Id, param_binding: &Binding) -> String { | |||
| } | |||
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| fn emit_primitive_extmodule<F: io::Write>( | |||
| ports: &SmallVec<[RRC<Port>; 10]>, | |||
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I think this could be just a slice type, to keep it slightly more generic?
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| ports: &SmallVec<[RRC<Port>; 10]>, | |
| ports: &[RRC<Port>], |
I assume SmallVec supports this "free" slice extraction, but I could be wrong!
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Yup! And the &[T] type is also compatible with references to normal vectors.
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This is so cool!! I'll read up about slice types, thanks for the suggestion!
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The relevant Deref impl is here: https://docs.rs/smallvec/latest/smallvec/struct.SmallVec.html#impl-Deref-for-SmallVec%3CA%3E
rachitnigam
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Feb 16, 2024
* First commit of what I believe is the fix for primitive extmodule port bug. Need to fix the code clone * fix code clone * Update tests. Need to manually test whether this will compile in FIRRTL * Fix formatting error * recover panic message for an inout port * Fixes from review comments
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I had a fault of omission in my previous primitive cell translation where the generated
extmoduledidn't list any of the input/output ports. I realized that the fix was pretty similar to the previous lines 80-106 so I extracted out that code into a function. I checked that the outputted FIRRTL files passed the FIRRTL to Verilog compiler, so this should be a fix!Please let me know if there's anything I can improve here :) Thank you in advance!