Add calyx-py AXI generator read channel
#1856
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TBD if this actually implements AXI correctly. There are currently some hacks in place (marked with todos) to get this to compile, namely some splicing that doesn't consider what we actually want to splice (it just takes [31:0]) as opposed to dynamically considering actual bits we want. A few other things that should be cleaned up eventually Need to create a cocotb testbench to test correctness
Maybe this shouldn't be here, but for now (having deleted my working directory earlier) putting it here
Simply run make from the cocotb directory and axi-read-tests will be executed
We tie ARID low in our manager
Prefixes should not contain trailing "_"
Got rid of "assert_val" and "block_transfer" groups and instead perform these things inside "do_ar_transfer", this is required because we cant assert valid before we drive the data correctly, so needs to happen in parallel. Currently: This seems to write 16 times to same place, this is due to hardcoding of 16 in ar transfer, not sure why address doesn't increment this is tbd (and next TODO)
This is part of read channel control sequence
Also reduces data bus width to 32
This solution, made for our load->compute->store scheme, simply increments the base_addr and curr_addr differently. This should make it easy to have multiple transactions, which this hardcoded does not support
TODO: Compare two, look at getting binary built. Look at improving *_use/modifying to fit needs better
This was referenced Jan 19, 2024
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| # TODO(nathanielnrn): Currently we assume that width is a power of 2. | ||
| # In the future we should allow for non-power of 2 widths, will need some | ||
| # splicing for this. | ||
| # See https://cucapra.slack.com/archives/C05TRBNKY93/p1705587169286609?thread_ts=1705524171.974079&cid=C05TRBNKY93 # noqa: E501 |
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All makes sense. For starters, one thing we could do here is just assert right at the beginning (i.e., in the build function) that the relevant parameters in the YXI document are all powers of two.
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* init commit of hardcoded axi wrapper for a 'main' kernel
* add axi-reads-calix
* hook up inputs to channels in the wrapper. tbd if this works
* Working calyx verison of AR and R
TBD if this actually implements AXI correctly.
There are currently some hacks in place (marked with todos)
to get this to compile, namely some splicing
that doesn't consider what we actually want to splice
(it just takes [31:0]) as opposed to dynamically considering actual
bits we want.
A few other things that should be cleaned up eventually
Need to create a cocotb testbench to test correctness
* Track output of compiled calyx read channel
Maybe this shouldn't be here, but for now (having deleted my
working directory earlier) putting it here
* update gitignore to get rid of sim_build and other cocotb artifacts
* Working make files for running cocotb tests
Simply run make from the cocotb directory and axi-read-tests
will be executed
* Add xID signals for cocotb compatability
We tie ARID low in our manager
* Fix prefix issue on cocotb axi test bench
Prefixes should not contain trailing "_"
* commit to repro 'make WAVES=1' cocotb error from axi-reads-calyx.futil
* axi-reads patch
* sync debug
* Add txn_len initialization to 16 in calyx program
* AXI Read fixed to get to read channel start
Got rid of "assert_val" and "block_transfer" groups
and instead perform these things inside "do_ar_transfer", this is
required because we cant assert valid before we drive the data
correctly, so needs to happen in parallel.
Currently: This seems to write 16 times to same place, this is due to
hardcoding of 16 in ar transfer, not sure why address doesn't
increment this is tbd (and next TODO)
* Add integer byte conversion for tests on Calyx AXI testharness
* WIP get reads to work. Add incr_curr_addr group
This is part of read channel control sequence
* remove .fst from tracking
* Add more data to testbench to make waveform viewing easier
* Reads seem to be terminating correctly at RLAST
* AR transfers seem to work, valid is high for 1 cycle
* Unreduced axi-reads-calyx.futil
Also reduces data bus width to 32
* Cocotb testbench now passes
* Formatted and passing axi-read-tests
* Reduce and comment axi-reads-calyx.futil
* remove axi-reads.v from being tracked
* add a todo
* add required ARPROT signal. This is hardcoded to be priviliged
* rename directories to yxi/axi-calyx
* initial commit of axi-writes-calyx, a copy of axi-reads-calyx
* WIP axi writes
* rename directories
* WIP imlpementing writes
* add testing for writes, note makefile is overwritten so now tests writes, not reads
* passing axi writes and testing
* init commit of hardcoded axi wrapper for a 'main' kernel
* add axi-reads-calix
* hook up inputs to channels in the wrapper. tbd if this works
* Working calyx verison of AR and R
TBD if this actually implements AXI correctly.
There are currently some hacks in place (marked with todos)
to get this to compile, namely some splicing
that doesn't consider what we actually want to splice
(it just takes [31:0]) as opposed to dynamically considering actual
bits we want.
A few other things that should be cleaned up eventually
Need to create a cocotb testbench to test correctness
* Track output of compiled calyx read channel
Maybe this shouldn't be here, but for now (having deleted my
working directory earlier) putting it here
* Working make files for running cocotb tests
Simply run make from the cocotb directory and axi-read-tests
will be executed
* Add xID signals for cocotb compatability
We tie ARID low in our manager
* Fix prefix issue on cocotb axi test bench
Prefixes should not contain trailing "_"
* commit to repro 'make WAVES=1' cocotb error from axi-reads-calyx.futil
* axi-reads patch
* sync debug
* Add txn_len initialization to 16 in calyx program
* AXI Read fixed to get to read channel start
Got rid of "assert_val" and "block_transfer" groups
and instead perform these things inside "do_ar_transfer", this is
required because we cant assert valid before we drive the data
correctly, so needs to happen in parallel.
Currently: This seems to write 16 times to same place, this is due to
hardcoding of 16 in ar transfer, not sure why address doesn't
increment this is tbd (and next TODO)
* Add integer byte conversion for tests on Calyx AXI testharness
* WIP get reads to work. Add incr_curr_addr group
This is part of read channel control sequence
* remove .fst from tracking
* Add more data to testbench to make waveform viewing easier
* Reads seem to be terminating correctly at RLAST
* AR transfers seem to work, valid is high for 1 cycle
* Unreduced axi-reads-calyx.futil
Also reduces data bus width to 32
* Cocotb testbench now passes
* Formatted and passing axi-read-tests
* Reduce and comment axi-reads-calyx.futil
* remove axi-reads.v from being tracked
* add a todo
* add required ARPROT signal. This is hardcoded to be priviliged
* rename directories to yxi/axi-calyx
* initial commit of axi-writes-calyx, a copy of axi-reads-calyx
* WIP axi writes
* rename directories
* WIP imlpementing writes
* add testing for writes, note makefile is overwritten so now tests writes, not reads
* passing axi writes and testing
* Work on full AXI wrapper, reads and compute works
* cleaned up combined futil and tests
* delete axi-reads* which is subsumed by axi-combined
* add axi-combined-tests.py
* remove axi-writes as it is subsumed by axi-combined
* formatting
* Update yxi/axi-calyx/axi-combined-calyx.futil
Co-authored-by: Adrian Sampson <asampson@cs.cornell.edu>
* formatting
* add sim.sh which goes from calyx to running tests
* simplify valid.in signals
* WIP: replace groups with reg invokes
* add python file that enables waveform (vcd/fst) generation
* formatting
* simplify valid.in signals
* WIP: replace groups with reg invokes
* Replaces register-init groups with invokes
* Formatting of invokes
* Replace reg groups with invokes in main
* Modify tests to account for base address != 0
* Separate base-address calyx-mem-address dependency
This solution, made for our load->compute->store scheme, simply
increments the base_addr and curr_addr differently.
This should make it easy to have multiple transactions, which this
hardcoded does not support
* move incrs into par block
* iitial axi-generator commit
* WIP get arread-channel working
* Finished ARREAD channel.
TODO: Compare two, look at getting binary built. Look at improving
*_use/modifying to fit needs better
* Create m_to_s_address_channel for {AR,AW} channels
* WIP: Add read channel
* Finished read_channel. Still need to fix #1850
* Finished read channels
* Remove read channel to break up into multiple PRs
* Add read channel back
---------
Co-authored-by: Rachit Nigam <rachit.nigam12@gmail.com>
Co-authored-by: Adrian Sampson <asampson@cs.cornell.edu>
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This PR is similar to #1855 in that via inspection I have tried to make sure that the output of the read channel matches the hardcoded read_channel.
Note that unlike #1855 this does not include a write channel because they are different enough to warrant completely different constructions in my mind (as opposed to a lot of shared construction between
ARandAWchannels seen in that PR)