SKARAB Test Model slx and scripts update for issue #200 #201
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Added platfor_devices to assist in platform lookup (to see if Ultra RAM supported).
Set memory to default to Block RAM if Ultra RAM selected but platform selected doesn't support this. NOTE: This is only applied to coeff generator. Top level coeff gen block does not yet change to Block RAM if defalut mem_type changed due to non-support of selected platform. pfb_fir_taps needs to be updated.
This all needs to be retested.
All seems to work.
Otherwise casperfpga fails at get_system_info() this doesnt reflect the correct memory map as the ethernet core is actually connected to the block diagram axi4lite interface.
Rolled bus library back. Copied out block. Removed library link. Changed parameter to have Ultra RAM as an option. Removed old block from library and copied in new. Saved library. Tested pfb_fir_generic works with the new block as required.
Data taps and coefficient storage implementation are now separate options. Distributed memory removed as an option as scripts can't draw these properly as the ports change. (This could be added with a little effort but would only make sense for small PFBs). Removed the checks of the implementation target at a high level as checks already done at a low level.
Block and init script to allow Ultra RAM buffer to be used.
Block parameter option added and init script support.
A number of delay buffers in stages can now be implemented in URAM.
Passed down to internal biplex_core.
Delays can now be implemented in Ultra RAM for a certain number of stages. The "FFT Stages" parameter default value of -1 was changed to 0 as the script was not able to execute correctly with -1.
Ultra RAM does not permit initialisaion values so cannot be used dto store coefficients. Removed this options from the PFB FIR.
Ultra ram nov22
We have updated the block diagram to meet timing as well as added in timing constraints to the xdc file. This design now reflects Amits initial design.
The tx_ip address port has been removed as it is set from software The correct mask script is now associated with the 100gbe core
jasper.per failed to generate when the core didnt have any paramters in the yellow block, there is now a dummy parameter which will be used when farm mode support is added to the core.
the alveo 100gbe doesnt take a port parameter as there is only 1 port on the au50, this is commented out in the scripts, but if we add support for the au280 it will need to be relooked at.
1. Adde the 100gbe yellow block parameters back in as this was causing gen_system_info to fail. 2. Added support for Farm mode, ei the LUT for dest ips and MAC
…rog' block. Known Issue: Memory has to be 'dual port' for BRAM and Ultra RAM selection. Chnaging to 'single port' generates an error. Also - no support for 'Distributed memory' added - this would require modification of other scripts. If 'Distributed memory' is required, it would be necessary to comment out the init script and manually set the memory type in the block.
Farm mode is untested and requires the bram for the LUT to be prepopulated at compile time, there is no support for this from the toolflow, so a work- around will need to be implmented. The multicast is untested at this stage and will probably remain so, as we are moving on to other work.
Merging with -X ours as casper_library_delays won't merge right now as m2021a doesn't have delay_bram changes. I have saved these changes separately and will re-add it manually after this.
slx files are binary, so previous merge did not work as branch was made pre delay_bram update. So re-did the UltraRAM option to delay_bram. delay_wideband_prog and fft_wideband_real still seem to initialise correctly.
Ftd207 ultra ram
Removed fpg and other files that may not work in latest version and just kept the script files for now. This should suffice for the CASPER 2023 workshop.
|
@AdamI75 @wnew Thank you very much! It looks like we're picking up a few other SARAO m2021a commits as well (ultraram support, alveo 100g). They all look very welcome, I just want to go over them quickly to make sure there won't be any upcoming conflicts, then will complete the pull request. Thanks again! |
jkocz
reviewed
Aug 3, 2023
There was a problem hiding this comment.
Looks mostly good - and ultraram support is definitely something we want. There are a couple of changes in the 100gb yellow block (in the .py separate from the alveo_100gb hdl) that look like it removes RFSoC from the factory, and change some of the parameter names. - This will need to be updated before / during merge to make sure everything remains functional.
|
@jkocz thanks for letting us know. Yes, it is possible that some of the RFSoC info was removed during the 100GbE UKRI RAL core updates. I agree that the RFSoC needs to remain, apologies if this was nuked. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
@jkocz Wesley and I have removed all the obsolete slx files, unused fpg files and other confusing files within the jasper_library/test_model folder. I will be honest and say that I have not compiled these files to test fully, as we just don't have the time. The idea is that the user chooses the slx file from the test_model folder and uses the "script" folder that has the same name as the slx file to program, setup registers and snap shots. The tutorials_devel folder has all the relevant files though, so these scripts are more for the developers than the general CASPER users. Let me know if anyone reports issues related to the SKARAB files and we will do our best to test this and fix it properly. SKARAB tutorials and test model files were baselined and tested using Matlab R2018a and not really R2021a, so there may be some issues still. I know that some SKARAB spectrometer and ADC tutorials may have issues with R2021a. Anyway, this should be fine for the CASPER 2023 conference/workshop clean up.