WIP: USB PD support

.github/workflows/build.yml

@@ -25,10 +25,12 @@ jobs:
           rustup target add riscv32imac-unknown-none-elf
           rustup target add riscv32imafc-unknown-none-elf
           rustup target add riscv32i-unknown-none-elf
-      # - name: Fetch Deps
-      #  run: |
-      #    mkdir -p ../ch32-data/build/
-      #    cd ../ch32-data/build/
-      #    git clone https://github.com/ch32-rs/ch32-metapac.git
+      - name: Fetch Deps
+        # if this is a pull request
+        if: github.event_name == 'pull_request'
+        run: |
+          mkdir -p ../ch32-data/build/
+          cd ../ch32-data/build/
+          git clone https://github.com/ch32-rs/ch32-metapac.git
       - name: Build Only
         run: ./ci.sh

Cargo.toml

@@ -16,11 +16,8 @@ license = "MIT OR Apache-2.0"
 ch32-metapac = { features = [
     "memory-x",
     "rt",
-], git = "https://github.com/ch32-rs/ch32-metapac.git", tag = "ch32-data-3e5718747ccd2dc429be042f893ed90b581ce265" }
-#ch32-metapac = { features = [
-#    "memory-x",
-#    "rt",
-#], path = "../ch32-data/build/ch32-metapac" }
+], git = "https://github.com/ch32-rs/ch32-metapac.git", tag = "ch32-data-9839bac87ce756ab19b09c03d89644be401a1c10" }
+# ch32-metapac = { features = ["memory-x","rt"], path = "../ch32-data/build/ch32-metapac" }
 
 qingke = { version = "0.2.0", features = ["critical-section-impl"] }
 qingke-rt = "0.2.1"
@@ -40,10 +37,10 @@ defmt = { version = "0.3.5", optional = true }
 embassy-sync = { version = "0.5.0", optional = true }
 embassy-futures = { version = "0.1.1", optional = true }
 embassy-time-driver = { version = "0.1.0", features = [
-    "tick-hz-10_000",
+    "tick-hz-1_000_000",
 ], optional = true }
 embassy-time = { version = "0.3.0", features = [
-    "tick-hz-10_000",
+    "tick-hz-1_000_000",
 ], optional = true }
 embassy-usb-driver = "0.1.0"
 
@@ -59,12 +56,10 @@ sdio-host = "0.5.0"
 [build-dependencies]
 ch32-metapac = { features = [
     "metadata",
-], git = "https://github.com/ch32-rs/ch32-metapac.git", tag = "ch32-data-3e5718747ccd2dc429be042f893ed90b581ce265" }
-#ch32-metapac = { default-features = false, features = [
-#    "metadata",
-#], path = "../ch32-data/build/ch32-metapac" }
+], git = "https://github.com/ch32-rs/ch32-metapac.git", tag = "ch32-data-9839bac87ce756ab19b09c03d89644be401a1c10" }
+# ch32-metapac = { default-features = false, features = ["metadata"], path = "../ch32-data/build/ch32-metapac" }
 
-proc-macro2 = "1.0.78"
+proc-macro2 = "1.0.84"
 quote = "1.0"
 
 [features]

README.md

@@ -33,8 +33,8 @@ For a full list of chip capabilities and peripherals, check the [ch32-data](http
 | V1     |        | ✅      | ✅  | ✅   | ✅   | ✅  | ✅  | ✅  | ✅         | ❓   |     | ❓  | ✅    | |
 | V0     |        | ✅      | ✅  | ✅   | ✅   | ✅  | ✅  | ✅  | ✅         | ❓   |     | ❓  | ✅    | |
 | X0     |        | ✅      | ✅  | ✅   | ✅   | ✅  | ❓  | ✅  | ✅         | ✅   |     | ✅  |       | |
-| L0     |        | ✅      | ✅  | ✅   | ✅   | ✅  | ❓  | ✅  | ✅         | ❓   |     | ❓  |       | |
-| CH641  |        | ✅      | ✅  | ✅   | ❓   | N/A | ❓  | ❓  | ✅         | ❓   |     | ❓  | ✅    | |
+| L1     |        | ✅      | ✅  | ✅   | ✅   | ✅  | ❓  | ✅  | ✅         | ❓   |     | ❓  |       | |
+| CH641  |        | ✅      | ✅  | ✅   | ❓   | N/A | ❓  | ✅  | ✅         | ❓   |     | ❓  | ✅    | ISP |
 | CH643  | TODO   |         |     |      |      |     |     |     |            |      |     |     |       | |
 
 - ✅ : Expected to work

build.rs

@@ -388,6 +388,9 @@ fn main() {
         // USB is splitted into multiple impls
         (("usbd", "DP"), quote!(crate::usbd::DpPin)),
         (("usbd", "DM"), quote!(crate::usbd::DmPin)),
+        // USBPD, handled by usbpd/mod.rs
+        //(("usbpd", "CC1"), quote!(crate::usbpd::Cc1Pin)),
+        //(("usbpd", "CC2"), quote!(crate::usbpd::Cc2Pin)),
     ]
     .into();
 

src/adc.rs

@@ -1,16 +1,19 @@
-//! ADC
-//!
-//! Max clock: 14MHz for CHFV2x_V3x
+//! ADC, Analog to Digital Converter
 
 #![macro_use]
 
-use ch32_metapac::adc::vals;
 use embassy_sync::waitqueue::AtomicWaker;
 
+use crate::pac::adc::vals;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::{into_ref, peripherals, Peripheral};
 
+/// ADC bit resolution
+#[cfg(any(adc_v0, adc_ch641))]
+pub const ADC_MAX: u32 = (1 << 10) - 1;
+#[cfg(not(any(adc_v0, adc_ch641)))]
 pub const ADC_MAX: u32 = (1 << 12) - 1;
+
 // No calibration data, voltage should be 1.2V (1.16 to 1.24)
 pub const VREF_INT: u32 = 1200;
 
@@ -289,4 +292,88 @@ mod ch_internal {
     }
 }
 
+#[cfg(adc_ch641)]
+mod ch_internal {
+    use super::*;
+    use crate::pac::EXTEND;
+
+    // FIXME: move peripherals and pins
+
+    /// Differential input current sampling
+    pub struct Isp {
+        _marker: core::marker::PhantomData<()>,
+    }
+
+    #[derive(Default)]
+    pub struct IspConfig {
+        /// DC bias is about 400 in raw ADC sample value.
+        pub dc_bias: bool,
+    }
+
+    impl Isp {
+        pub fn new_non_inverting(in_positive: impl NonInvertingPin, config: IspConfig) -> Self {
+            in_positive.set_as_isp_pin();
+            EXTEND.ctlr2().modify(|w| {
+                w.set_isp_ps(in_positive.pin_sel());
+                w.set_isp_ns(true); // use GND
+                w.set_isp_ae(true);
+                w.set_isp_be(config.dc_bias);
+            });
+            Isp {
+                _marker: core::marker::PhantomData,
+            }
+        }
+
+        // PB6/PA6, PB7
+        pub fn new(in_positive: impl NonInvertingPin, in_negative: impl InvertingPin, config: IspConfig) -> Self {
+            in_positive.set_as_isp_pin();
+            in_negative.set_as_isp_pin();
+            EXTEND.ctlr2().modify(|w| {
+                w.set_isp_ps(in_positive.pin_sel());
+                w.set_isp_ns(false); // true: use GND; false: use PB7
+                w.set_isp_ae(true);
+                w.set_isp_be(config.dc_bias);
+            });
+            Isp {
+                _marker: core::marker::PhantomData,
+            }
+        }
+    }
+
+    pub trait NonInvertingPin {
+        fn set_as_isp_pin(&self) {}
+        fn pin_sel(&self) -> bool;
+    }
+    pub trait InvertingPin {
+        fn set_as_isp_pin(&self) {}
+    }
+    impl NonInvertingPin for peripherals::PA6 {
+        fn pin_sel(&self) -> bool {
+            true
+        }
+    }
+    // aka. ISP pin
+    impl NonInvertingPin for peripherals::PB6 {
+        fn pin_sel(&self) -> bool {
+            false
+        }
+    }
+    impl InvertingPin for peripherals::PB7 {}
+
+    impl<T: Instance> AdcPin<T> for Isp {}
+    impl<T: Instance> SealedAdcPin<T> for Isp {
+        fn channel(&self) -> u8 {
+            8
+        }
+    }
+
+    pub struct VhvDiv5;
+    impl<T: Instance> AdcPin<T> for VhvDiv5 {}
+    impl<T: Instance> SealedAdcPin<T> for VhvDiv5 {
+        fn channel(&self) -> u8 {
+            15
+        }
+    }
+}
+
 pub use ch_internal::*;

src/exti.rs

@@ -133,7 +133,8 @@ impl<'a> ExtiInputFuture<'a> {
                 // stride: 2, len: 15, 8 lines
                 afio.exticr().modify(|w| w.set_exti(pin, port));
             }
-            #[cfg(afio_v3)]
+            // V1, V2, V3, L1
+            #[cfg(any(afio_v3, afio_l1))]
             {
                 // AFIO_EXTICRx
                 // stride: 4, len: 4, 16 lines
@@ -144,6 +145,11 @@ impl<'a> ExtiInputFuture<'a> {
                 // stride: 2, len: 15, 24 lines
                 afio.exticr(pin / 16).modify(|w| w.set_exti(pin % 16, port));
             }
+            #[cfg(afio_ch641)]
+            {
+                // single register
+                afio.exticr().modify(|w| w.set_exti(pin, port != 0));
+            }
 
             // See-also: 7.4.3
             exti.intenr().modify(|w| w.set_mr(pin, true)); // enable interrupt

src/i2c.rs

@@ -138,8 +138,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
         // CH32V2, CH32V3
         scl.set_as_af_output(AFType::OutputOpenDrain, Speed::High);
         sda.set_as_af_output(AFType::OutputOpenDrain, Speed::High);
-        //sda.set_as_af_output(AFType::OutputPushPull, Speed::High);
-        //scl.set_as_af_output(AFType::OutputPushPull, Speed::High);
 
         let mut this = Self {
             _peri: peri,

src/lib.rs

@@ -75,6 +75,9 @@ pub mod usb;
 #[cfg(usbd)]
 pub mod usbd;
 
+#[cfg(usbpd)]
+pub mod usbpd;
+
 #[cfg(feature = "embassy")]
 pub mod embassy;
 

src/macros.rs

@@ -14,7 +14,7 @@ macro_rules! dma_trait {
 
 macro_rules! pin_trait {
     ($signal:ident, $instance:path) => {
-        pub trait $signal<T: $instance, const REMAP: u8>: crate::gpio::Pin {}
+        pub trait $signal<T: $instance, const REMAP: u8 = 0>: crate::gpio::Pin {}
     };
 }
 macro_rules! pin_trait_impl {

src/rcc/ch641.rs

@@ -6,7 +6,7 @@
 use core::ops;
 
 use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler, Sw as Sysclk};
-use crate::pac::{AFIO, FLASH, RCC};
+use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
 pub const HSI_FREQUENCY: Hertz = Hertz(24_000_000);

src/usart/mod.rs

@@ -1027,6 +1027,20 @@ fn configure(
     Ok(())
 }
 
+impl<'d, T: Instance> core::fmt::Write for UartTx<'d, T, Blocking> {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result {
+        self.blocking_write(s.as_bytes()).map_err(|_| core::fmt::Error)?;
+        Ok(())
+    }
+}
+impl<'d, T: Instance> core::fmt::Write for Uart<'d, T, Blocking> {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result {
+        self.blocking_write(s.as_bytes()).map_err(|_| core::fmt::Error)?;
+        Ok(())
+    }
+}
+
+
 // Peripheral traits
 struct State {
     rx_waker: AtomicWaker,