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Connect-by-name has no vpiHighConn #3958
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pieter3d this is working just fine:
|
You need to look at the elaborated tree |
Are you sure that's right? the port "clk" has both the the HighConn and LowConn vpiActual as the inner net of the sub module - |
It's more obvious when the same module is connected different ways (all logically equivalent): module sub (
input logic clk
);
endmodule
module test;
logic clk;
sub sub0 ( .* );
sub sub1 ( .clk );
sub sub2 ( .clk (clk) );
endmodule |
UHDM dump of module sub (
input logic clk
);
endmodule
module test;
logic clk;
logic clk_wire;
sub sub0 ( .* );
sub sub1 ( .clk );
sub sub2 ( .clk (clk) );
sub sub3 ( .clk (clk_wire) );
endmodule
Interestingly, even sub2 gets an incorrect High_conn. Only sub3 has the right one, there is some kind of name collision happening somewhere, it seems. |
I poked around some in NetlistElaboration.cpp, thanks for the suggestion. At the point where UHDM::any* con =
((UHDM::design *)((uhdm_handle *)vpi_design)->object)
->TopModules()
->at(0)
->Modules() // name is "sub0"
->at(0)
->Ports()->at(0)->High_conn();
UHDM::ref_obj* o = (UHDM::ref_obj*)con;
printf("debug: %d %d %s\n",
o->Actual_group()->VpiType(),
o->Actual_group()->VpiLineNo(),
std::string(o->Actual_group()->VpiName()).c_str()); shows the So either the elaborated module gets replaced, or I am not looking at the right elaborated tree somehow. I don't think the High_conn itself is getting overwritten later, based on some debug prints and watching addresses in a debugger, but I am not 100% sure. So - not quite sure yet where the issues lies. |
Ok, making some progress. The High_conn's During write-out, if the net name matches any local nets, it gets replaced. |
The instStack_ has to be popped temporarily while binding high_conn so is skips the current module scope. |
Yeah that's kinda what I figured, but the Listener classes need some new state to know to do that, i.e. when they are processing a High_conn |
Set a bp in the bind function, check the stack, you should see the high conn relation traversal, the python code generator in scripts/ needs to change to pop and push back the context before and after the traversal of that particular relation |
Yes, but that's all c++ code... Where does python come into this? |
Most of the C++ code is auto generated by Python |
Dumping the UHDM for that shows this (instance only):
So at least two things look wrong to me:
clk
but it's a valid connect-by-name constructdata_out
output is totally missing, the port has a blank name.The text was updated successfully, but these errors were encountered: