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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 107 repositories
  • chisel-nix Public

    Nix scripts used to manage the chisel projects.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 20 1 0 1 Updated Sep 21, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 52 Apache-2.0 39 86 54 Updated Sep 21, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 65 Apache-2.0 36 66 10 Updated Sep 21, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Sep 21, 2024
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 3 Apache-2.0 2 11 2 Updated Sep 21, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 285 ISC 75 45 (5 issues need help) 23 Updated Sep 21, 2024
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 354 Apache-2.0 68 48 (2 issues need help) 1 Updated Sep 20, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,921 Apache-2.0 589 306 (1 issue needs help) 156 Updated Sep 20, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 112 Apache-2.0 21 17 21 Updated Sep 20, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Sep 20, 2024
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