CHIPS Alliance

All

110 repositories

Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•76•263•20•6•Updated Feb 4, 2025Feb 4, 2025
synlig
Public
SystemVerilog synthesis tool
Verilog
•
Apache License 2.0
•23•177•69•10•Updated Feb 4, 2025Feb 4, 2025
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
•
Apache License 2.0
•612•4.1k•313•176•Updated Feb 4, 2025Feb 4, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•5•11•18•6•Updated Feb 4, 2025Feb 4, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•2•5•0•0•Updated Feb 4, 2025Feb 4, 2025
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•47•100•112•57•Updated Feb 4, 2025Feb 4, 2025
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•45•83•81•13•Updated Feb 4, 2025Feb 4, 2025
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•1•9•7•5•Updated Feb 3, 2025Feb 3, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•75•306•46•34•Updated Feb 3, 2025Feb 3, 2025
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•22•15•11•7•Updated Feb 3, 2025Feb 3, 2025
t1
Public
Scala
•
Apache License 2.0
•24•133•17•27•Updated Feb 3, 2025Feb 3, 2025
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•29•51•25•17•Updated Feb 2, 2025Feb 2, 2025
chisel-nix
Public
Nix template for the chisel-based industrial designing flows.
Nix
•3•34•0•1•Updated Feb 2, 2025Feb 2, 2025
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•2•13•6•0•Updated Jan 31, 2025Jan 31, 2025
chips-alliance-website
Public
SCSS
•
MIT License
•4•3•8•8•Updated Jan 31, 2025Jan 31, 2025
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•38•253•24•3•Updated Jan 31, 2025Jan 31, 2025
chisel-interface
Public
The 'missing header' for Chisel
Scala
•1•18•0•0•Updated Jan 30, 2025Jan 30, 2025
rocket-chip
Public
Rocket Chip Generator
chisel scala rocket-chip chip-generator riscv rtl
Scala
•
Other
•1.1k•3.3k•233•64•Updated Jan 30, 2025Jan 30, 2025
chisel-template
Public template
A template project for beginning new Chisel work
Scala
•
The Unlicense
•189•611•12•2•Updated Jan 30, 2025Jan 30, 2025
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•3•13•11•0•Updated Jan 29, 2025Jan 29, 2025
firtool-resolver
Public
Scala
•1•2•0•1•Updated Jan 29, 2025Jan 29, 2025
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
•
Other
•222•1.5k•488•21•Updated Jan 29, 2025Jan 29, 2025
synlig-logs
Public
SystemVerilog
•0•0•0•0•Updated Jan 27, 2025Jan 27, 2025
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Scala
•3•13•0•1•Updated Jan 26, 2025Jan 26, 2025
veer-el2-dashboard
Public
HTML
•1•0•0•0•Updated Jan 22, 2025Jan 22, 2025
rocket-pcb
Public
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
•
Apache License 2.0
•2•7•0•1•Updated Jan 22, 2025Jan 22, 2025
rocket-pcblib
Public
Apache License 2.0
•0•1•0•0•Updated Jan 22, 2025Jan 22, 2025
verible-formatter-action
Public
SystemVerilog
•
Apache License 2.0
•8•10•3•0•Updated Jan 21, 2025Jan 21, 2025
rocket-chip-inclusive-cache
Public
An RTL generator for a last-level shared inclusive TileLink cache controller
Scala
•
Apache License 2.0
•20•15•7•4•Updated Jan 17, 2025Jan 17, 2025
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
•
GNU Lesser General Public License v3.0
•633•35•0•1•Updated Jan 16, 2025Jan 16, 2025