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1. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog

2. CTSRD-CHERI/TestRIG CTSRD-CHERI/TestRIG Public

   Testing processors with Random Instruction Generation

   Python 29 8

3. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

4. riscv-dv riscv-dv Public

   Forked from chipsalliance/riscv-dv

   Random instruction generator for RISC-V processor verification

   Python

5. praesidio-sdk praesidio-sdk Public

   Complete RISC-V toolchain to evaluate physically isolated enclaves

   Python 1

6. tiny-factorizer tiny-factorizer Public

   Based on: https://github.com/TinyTapeout/tt04-verilog-demo

   Verilog