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hi
I can make my code working to generate the verilog file. please help
package test
import chisel3._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
object testMain extends App {
(new ChiselStage).execute(
Array("--target-dir", "generated/and"),
Seq(ChiselGeneratorAnnotation(() => new AND))
)
}
[info] compiling 1 Scala source to /Users/peter/Desktop/chisel-template/target/scala-2.13/test-classes ...
[error] /Users/peter/Desktop/chisel-template/src/test/scala/testMain.scala:3:8: object ChiselStage is not a member of package chisel3.stage
[error] import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
[error] ^
[error] /Users/peter/Desktop/chisel-template/src/test/scala/testMain.scala:6:8: not found: type ChiselStage
[error] (new ChiselStage).execute(
[error] ^
[error] two errors found
[error] (Test / compileIncremental) Compilation failed
[error] Total time: 4 s, completed 16 Jan 2025, 20:19:46
thanks
The text was updated successfully, but these errors were encountered:
hi
I can make my code working to generate the verilog file. please help
thanks
The text was updated successfully, but these errors were encountered: