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Please provide the steps to reproduce the problem:
Try the following code:
//>usingscala"2.13.12"//>usingdep"org.chipsalliance::chisel:6.3.0"//>usingplugin"org.chipsalliance:::chisel-plugin:6.3.0"//>usingoptions"-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"importchisel3._importchisel3.simulator.EphemeralSimulator._// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._import_root_.circt.stage.ChiselStageclassFooextendsModule {
valio=FlatIO(newBundle {
valin=Input(UInt(8.W))
valout=Output(UInt(8.W))
})
valdelay=RegNext(io.in)
io.out := delay
}
objectMainextendsApp {
println(
ChiselStage.emitSystemVerilog(
gen =newFoo,
firtoolOpts =Array("-disable-all-randomization", "-strip-debug-info")
)
)
simulate(newFoo) { c =>
c.io.in.poke(12.U)
c.clock.step()
c.io.out.peek()
}
}
What is the current behavior?
Verilog generates just fine, but ChiselSim throws an exception:
Exception in thread "main" java.util.NoSuchElementException: key not found: Foo.in: IO[UInt<8>]
at scala.collection.immutable.Map$Map4.apply(Map.scala:535)
at chisel3.simulator.package$AnySimulatedModule.port(package.scala:36)
at chisel3.simulator.PeekPokeAPI$testableData.poke(PeekPokeAPI.scala:116)
at chisel3.simulator.PeekPokeAPI$testableData.poke(PeekPokeAPI.scala:111)
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Try the following code:
What is the current behavior?
Verilog generates just fine, but ChiselSim throws an exception:
What is the expected behavior?
This should work just fine
Please tell us about your environment:
Other Information
Derived from question on Gitter1.
What is the use case for changing the behavior?
Correct behavior
Footnotes
https://matrix.to/#/!jSbgpvvpsPbLpsLZOC:matrix.org/$a1ygVO22ceENy_lUNaTNuqOv-cGaM1oa2IxVSsRKPQ8?via=matrix.org&via=gitter.im&via=mumblingdrunkard.com ↩
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