ChiselSim waveforms

[HakamAtassi]

Hello!

I feel like I'm not the first to ask, but I haven't found anything regarding this as an open issue so I'll ask nonetheless.

ChiselSim. Waveforms. Yes or no?

Can I write chisel/scala tests and dump a VCD like ChiselTest?

[zhutmost]

A simple answer is: yes

[HakamAtassi]

A simple answer is: yes

How? Is there a native way of doing that or does it involve tywaves?

[zhutmost]

Enable traceEnabled when yourunElaboratedModule during simulation. See

chisel/src/main/scala/chisel3/simulator/package.scala

Line 92 in 8f00067

traceEnabled: Boolean = false,

And I have some wrapper code to make it much easier. See my example here.

[jackkoenig]

It's not exposed with the existing EphemeralSimulator, but there is work towards simpler user APIs like #4209 which should make this easier.

[edwardcwang]

On vanilla Chisel 6.5 this ended up requiring two separate hacks against EphemeralSimulator:

1. https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L44
   Inserting traceStyle = Some(verilator.Backend.CompilationSettings.TraceStyle.Vcd(traceUnderscore = true)) into the backendSpecificCompilationSettings of the DefaultSimulator.

2. https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L31
   The above was not enough as it added support for tracing but did not actually call the functions to enable & start the dumping.
   Hacking the simulate() method to insert a call to module.controller.setTraceEnabled(true) to actually enable the dump of the .vcd file.

Third bonus hack: use the local test_run_dir directory (from older versions of Chisel) instead of a temporary one which gets deleted.
https://github.com/edwardcwang/decoupled-serializer/blob/master/src/main/scala/VCDHackedEphemeralSimulator.scala#L61