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Designs that Work by changing MMCME2 primitive to PLL:
As of this writing none of the designs in FPGA Graphics will work using symbiflow unless the MMCME2_BASE primitive from clock_gen_480p.sv is converted to a PLL. Symbiflow currently does not offer support for the MMCME2_BASE primitive. A techmap for this primitive is being built and progress on the techmap can be tracked in symbiflow-arch-defs issue #2246. I was able to get many designs to work on the current toolchain by changing the MMCME2_BASE into a PLLE2_ADV and by modifying the parameters MULT_MASTER, DIV_MASTER, DIV_PIX, and IN_PERIOD in clock_gen_480p to be 9, 1, 36, and 10 respectively.
These are the designs that worked making only the above changes:
Once Issues with the MMCME2_ADV module are fixed (see issue #2248) and a tech map for the MMCME2_BASE is finished all of the above designs should work in symbiflow without flaw.
Designs that work only when certain design files are converted from SV to V:
There are a few designs in Project F that only work when the designs are converted from SystemVerilog to Verilog. This issue may be due in part to symbiflows inability to work with SV designs that pass single words of a Multi bit array between modules (see issue #170). Other causes for this peculiarity are being explored.
For now I have been able to get these designs working in symbiflow only after converting certain SV files to V using sv2v:
Ad Astra:
If these designs are not converted to verilog the display will show only a set of verticle lines that are partial prints of the letters that should be displayed as well as the background starfield.
Hello both in english and japenies work if just top_hello_en.sv and top_hello_jp.sv are converted to verilog using sv2v.
Top great version 1 works if top_greet_v1.sv is converted to verilog.
Top great final version works if top_greet.sv is converted to verilog.
Lines and Triangles:
Nothing will be displayed on the screen if the top modules are not converted to verilog.
Top line module works if top_line.sv is converted to verilog.
Designs that do not work at all:
I have been unable to get any of these designs working in symbiflow by using either of the two above methods. These designs generate faulty bitstreams and nothing is shown on the display when the bitstream is downloaded to the board. It is worth mentioning that all of these designs do work in vivado just not in symbiflow:
Lines and Triangles:
Top cube
Top Triangle
All of the Designs in 2D shapes generate faulty bitstreams when using the symbiflow toolchain.
The text was updated successfully, but these errors were encountered:
This issue is meant to serve as a log for the designs in project F that work and fail using the symbiflow toolchain.
Hello:
All of the designs in this module work without any modifications to the designs. These designs are currently being ported into symbiflow PR #181:
All Designs in Hello Arty 1
All designs in Hello Arty 2
All designs in Hello Arty 3
Designs that Work by changing MMCME2 primitive to PLL:
As of this writing none of the designs in FPGA Graphics will work using symbiflow unless the MMCME2_BASE primitive from clock_gen_480p.sv is converted to a PLL. Symbiflow currently does not offer support for the MMCME2_BASE primitive. A techmap for this primitive is being built and progress on the techmap can be tracked in symbiflow-arch-defs issue #2246. I was able to get many designs to work on the current toolchain by changing the MMCME2_BASE into a PLLE2_ADV and by modifying the parameters MULT_MASTER, DIV_MASTER, DIV_PIX, and IN_PERIOD in clock_gen_480p to be 9, 1, 36, and 10 respectively.
These are the designs that worked making only the above changes:
All designs in FPGA Graphics
All designs in Pong
All designs in Hardware Sprites
All designs in Framebuffers
All designs in Life on Screen
Only these designs work from Ad Astra:
Once Issues with the MMCME2_ADV module are fixed (see issue #2248) and a tech map for the MMCME2_BASE is finished all of the above designs should work in symbiflow without flaw.
Designs that work only when certain design files are converted from SV to V:
There are a few designs in Project F that only work when the designs are converted from SystemVerilog to Verilog. This issue may be due in part to symbiflows inability to work with SV designs that pass single words of a Multi bit array between modules (see issue #170). Other causes for this peculiarity are being explored.
For now I have been able to get these designs working in symbiflow only after converting certain SV files to V using sv2v:
Ad Astra:
If these designs are not converted to verilog the display will show only a set of verticle lines that are partial prints of the letters that should be displayed as well as the background starfield.
Lines and Triangles:
Nothing will be displayed on the screen if the top modules are not converted to verilog.
Designs that do not work at all:
I have been unable to get any of these designs working in symbiflow by using either of the two above methods. These designs generate faulty bitstreams and nothing is shown on the display when the bitstream is downloaded to the board. It is worth mentioning that all of these designs do work in vivado just not in symbiflow:
Lines and Triangles:
All of the Designs in 2D shapes generate faulty bitstreams when using the symbiflow toolchain.
The text was updated successfully, but these errors were encountered: