FF with clock enable and syncronous set/reset does not work

[litghost]

(* whitebox *)                                                                                                                                                                                                                                                                            
module FF(C, D, Q, CE, SR);                                                    
    parameter RESET_VALUE = 1'b0;                                                
                                                                               
    (* CLOCK *)                                                                
    input C;                                                                   
                                                                               
    (* SETUP = "C 10e-12" *)                                                   
    input D;                                                                   
                                                                               
    (* SETUP = "C 10e-12" *)                                                   
    input CE;                                                                  
                                                                               
    (* SETUP = "C 10e-12" *)                                                   
    input SR;                                                                  
                                                                               
    (* CLK_TO_Q = "C 10e-12" *)                                                
    output reg Q;                                                              
                                                                               
    always @(posedge C) begin                                                  
        if(SR) begin                                                           
            Q <= RESET_VALUE;                                                  
        end else if(CE) begin                                                  
            Q <= D;                                                            
        end                                                                    
    end                                                                        
                                                                               
endmodule    

This generates no clock annotations in the .model.xml for D/CE/SR. None of the current examples in the v2x documentation show how to make this work properly.

[mithro]

FYI - @mkurc-ant

[mithro]

https://python-symbiflow-v2x.readthedocs.io/en/latest/examples/vtr/dff/README.html#timings

Classical D-Flip-Flop test — SymbiFlow Verilog to XML (V2X) 0.0-551-g728f3b9 documentation

[mithro]

BTW - Your example looks valid and should probably also be a test case.