preprocessor placement gives error

[jefflfree]

Describe the bug

If I put `else in the middle of a module declaration (before ;) it fails. This is valid code.

To Reproduce
ifndef three module test1 else
module test2
`endif
;
endmodule

Did it reject valid code? or crash?
./verible-verilog-lint blah.v
blah.v:3:1: syntax error, rejected "`else" (syntax-error).
blah.v:7:1: syntax error, rejected "endmodule" (syntax-error).

Expected behavior

A clear and concise description of what you expected to happen. Citations to the
SystemVerilog-2017 Standard (LRM)
would help.

[tgorochowik]

Hi!

Thanks for filing this issue. Unfortunately Verible does not handle preprocessing very well at this point. Also see: #183

Having a proper preprocessor is certainly on our TODO list though