Merge pull request torvalds#193 in PROCESSOR-SDK/processor-sdk-linux …

…from plsdk-3118 to processor-sdk-linux-4.19.y * commit '05a2415c362774bc803bde7b67e230331358f337': (703 commits) Revert "HACK: ARM: dts: dra7-ipu-common: Revert to CMA pools for IPU early boots" clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference ARM: omap2+: hwmod: fix static checker warnings ARM: dts: dra71-evm: mark ldo0 regulator as always on arm64: dts: ti: k3-j721e: Disable MHDP in SoC- and enable in board-dt arm64: dts: ti: k3-j721: cleanup DP connector data arm64: dts: ti: k3-j721: move DP routing and pinmux to board DT file phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver Revert "HACK: phy: ti: j721e-wiz: override WIZ settings for DP" arm64: dts: ti: k3-j721e-proc-board-tps65917: Update wiz lane<n>-mode props arm64: dts: ti: k3-j721e-common-proc-board: Update wiz lane<n>-mode props dt-bindings: phy: ti,phy-j721e-wiz: Add "lane<n>-mode" properties dt-bindings: phy: Add PHY_TYPE_DP definition arm64: dts: ti: k3-j721e-main: Update wiz node compatible strings phy: ti: j721e-wiz: Use "ti,j721e-wiz-10g" or "ti,j721e-wiz-16g" compatible dt-bindings: phy: ti,phy-j721e-wiz: Add *-10g and *-16g to compatible ti_config_fragments: v8_baseport: Enable watchdog arm64: dts: ti: k3-j721e-main: Add MAIN domain watchdog entries watchdog: Add K3 RTI watchdog support ...
chombourger · Nov 7, 2019 · 02b8c9e · 02b8c9e
2 parents 8176796 + 05a2415
commit 02b8c9e
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diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
@@ -2503,8 +2503,8 @@
 			http://repo.or.cz/w/linux-2.6/mini2440.git
 
 	mitigations=
-			[X86,PPC,S390] Control optional mitigations for CPU
-			vulnerabilities.  This is a set of curated,
+			[X86,PPC,S390,ARM64] Control optional mitigations for
+			CPU vulnerabilities.  This is a set of curated,
 			arch-independent options, each of which is an
 			aggregation of existing arch-specific options.
 
@@ -2513,12 +2513,14 @@
 				improves system performance, but it may also
 				expose users to several CPU vulnerabilities.
 				Equivalent to: nopti [X86,PPC]
+					       kpti=0 [ARM64]
 					       nospectre_v1 [PPC]
 					       nobp=0 [S390]
 					       nospectre_v1 [X86]
-					       nospectre_v2 [X86,PPC,S390]
+					       nospectre_v2 [X86,PPC,S390,ARM64]
 					       spectre_v2_user=off [X86]
 					       spec_store_bypass_disable=off [X86,PPC]
+					       ssbd=force-off [ARM64]
 					       l1tf=off [X86]
 					       mds=off [X86]
 
@@ -2866,10 +2868,10 @@
 			(bounds check bypass). With this option data leaks
 			are possible in the system.
 
-	nospectre_v2	[X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2
-			(indirect branch prediction) vulnerability. System may
-			allow data leaks with this option, which is equivalent
-			to spectre_v2=off.
+	nospectre_v2	[X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for
+			the Spectre variant 2 (indirect branch prediction)
+			vulnerability. System may allow data leaks with this
+			option.
 
 	nospec_store_bypass_disable
 			[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt
@@ -178,3 +178,7 @@ HWCAP_ILRCPC
 HWCAP_FLAGM
 
     Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
+
+HWCAP_SSBS
+
+    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.txt b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.txt
@@ -5,11 +5,12 @@ The Cadence MHDP bridge is a DPI to DP bridge.
 
 Required properties:
 - compatible: should be "cdns,mhdp8546",
+  Use "ti,j721e-mhdp8546" for TI J7 SoCs.
 - reg: physical base address and length of the controller's registers,
 - clocks: DP bridge clock, it's used by the IP to know how to translate
 	a number of clock cycles into a time (which is used to comply
 	with DP standard timings and delays),
-- phys: see the Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+- phys: see the Documentation/devicetree/bindings/phy/phy-cadence-torrent.txt
 - phy-names: must be "dpphy"
 
 Required subnodes:

diff --git a/...evicetree/bindings/phy/phy-cadence-dp.txt → ...tree/bindings/phy/phy-cadence-torrent.txt b/...evicetree/bindings/phy/phy-cadence-dp.txt → ...tree/bindings/phy/phy-cadence-torrent.txt
@@ -1,12 +1,15 @@
-Cadence MHDP DisplayPort SD0801 PHY binding
-===========================================
+Cadence Torrent SD0801 PHY binding for DisplayPort
+===================================================
 
 This binding describes the Cadence SD0801 PHY hardware included with
 the Cadence MHDP DisplayPort controller.
 
 -------------------------------------------------------------------------------
 Required properties (controller (parent) node):
-- compatible	: Should be "cdns,dp-phy"
+- compatible	: Should be "cdns,torrent-phy"
+- clocks	: PHY reference clock. Must contain an entry in clock-names.
+		  See ../clocks/clock-bindings.txt for details.
+- clock-names	: Must be "refclk"
 - reg		: Defines the following sets of registers in the parent
 		  mhdp device:
 			- Offset of the DPTX PHY configuration registers
@@ -21,7 +24,7 @@ Optional properties:
 
 Example:
 	dp_phy: phy@f0fb030a00 {
-		compatible = "cdns,dp-phy";
+		compatible = "cdns,torrent-phy";
 		reg = <0xf0 0xfb030a00 0x0 0x00000040>,
 		      <0xf0 0xfb500000 0x0 0x00100000>;
 		num_lanes = <4>;

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.txt
@@ -1,7 +1,8 @@
 TI J721E WIZ (SERDES Wrapper)
 
 Required properties:
- - compatible: Should be "ti,j721e-wiz"
+ - compatible: Should be "ti,j721e-wiz-16g" for Sierra phy wrapper,
+	       or "ti,j721e-wiz-10g" for Torrent phy wrapper.
  - #address-cells : should be 2 to indicate the child node should use 2 cell
      for address
  - #size-cells: should be 2 to indicate the child node should use 2 cell for
@@ -32,6 +33,12 @@ clock bindings in Documentation/devicetree/bindings/clock/clock-bindings.txt
      Type-C spec states minimum CC pin debounce of 100 ms and maximum
      of 200 ms.
 
+ - lane<n>-mode, : Integer describing static lane usage for lane n. For
+     Sierra there may be properties for n = 0 and n = 1, for Torrent n = 0,
+     n = 1, n = 2, and n = 3. The constants to indicate the lane usage 
+     are defined in "include/dt-bindings/phy/phy.h". The lane is assumed
+     to be unused if the lane<n>-use property does not exist.
+
 Required subnodes:
  - Clock Subnode: WIZ node should have '3' subnodes for each of the clock
      selects it supports. The clock subnodes should have the following names
@@ -50,14 +57,16 @@ Required subnodes:
 
 Example: Example shows binding for SERDES_16G (Sierra SERDES with WIZ wrapper)
 serdes_wiz0: wiz@5000000 {
-	compatible = "ti,j721e-wiz";
+	compatible = "ti,j721e-wiz-16g";
 	#address-cells = <2>;
 	#size-cells = <2>;
 	power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 	clocks = <&k3_clks 292 5>;
 	num-lanes = <2>;
 	#reset-cells = <1>;
 	ranges;
+	lane0-mode = <PHY_TYPE_PCIE>;
+	lane1-mode = <PHY_TYPE_PCIE>;
 
 	pll0_refclk: pll0_refclk {
 		clocks = <&k3_clks 292 11>, <&cmn_refclk>;

diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.txt b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.txt
@@ -0,0 +1,18 @@
+Texas Instruments RTI (Real Time Interrupt) module. RTI is used for
+implementing a watchdog on TI SoCs.
+
+Required properties:
+	compatible	= "ti,rti-wdt";
+	reg		= Physical IO space for RTI
+	clocks		= Functional clock for the RTI
+
+Example:
+
+main_rti0: rti@2200000 {
+	compatible = "ti,rti-wdt";
+	reg = <0x0 0x2200000 0x0 0x100>;
+	clocks = <&k3_clks 252 1>;
+	power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+	assigned-clocks = <&k3_clks 252 1>;
+	assigned-clock-parents = <&k3_clks 252 5>;
+};
diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt
@@ -302,7 +302,7 @@ beneath or above the path of another overlay lower layer path.
 
 Using an upper layer path and/or a workdir path that are already used by
 another overlay mount is not allowed and may fail with EBUSY.  Using
-partially overlapping paths is not allowed but will not fail with EBUSY.
+partially overlapping paths is not allowed and may fail with EBUSY.
 If files are accessed from two overlayfs mounts which share or overlap the
 upper layer and/or workdir path the behavior of the overlay is undefined,
 though it will not result in a crash or deadlock.

diff --git a/Makefile b/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 4
 PATCHLEVEL = 19
-SUBLEVEL = 73
+SUBLEVEL = 79
 EXTRAVERSION =
 NAME = "People's Front"
 

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
@@ -1586,8 +1586,9 @@ config ARM_PATCH_IDIV
 	  code to do integer division.
 
 config AEABI
-	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
-	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
+	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
+		!CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
+	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
 	help
 	  This option allows for the kernel to be compiled using the latest
 	  ARM ABI (aka EABI).  This is only useful if you are using a user

diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
@@ -151,3 +151,5 @@
 	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi
@@ -140,3 +140,5 @@
 &vip2 {
 	status = "okay";
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -668,3 +668,5 @@
 	status = "okay";
 	memory-region = <&dsp2_memory_region>;
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
@@ -727,3 +727,5 @@
 &bb2d {
 	status = "okay";
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/dra7-ipu-common-early-boot.dtsi b/arch/arm/boot/dts/dra7-ipu-common-early-boot.dtsi
@@ -38,6 +38,11 @@
 	ti,no-reset-on-init;
 };
 
+&ipu2_memory_region {
+	/delete-property/ reusable;
+	no-map;
+};
+
 &ipu2 {
 	ti,no-idle-on-init;
 	ti,no-reset-on-init;
@@ -64,6 +69,11 @@
 	ti,no-reset-on-init;
 };
 
+&ipu1_memory_region {
+	/delete-property/ reusable;
+	no-map;
+};
+
 &ipu1 {
 	ti,no-idle-on-init;
 	ti,no-reset-on-init;

diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
@@ -115,6 +115,8 @@
 				regulator-name = "lp8733-ldo0";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
 			lp8733_ldo1_reg: ldo1 {
@@ -321,3 +323,5 @@
 	status = "okay";
 	memory-region = <&dsp1_memory_region>;
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
@@ -163,3 +163,5 @@
 	status = "okay";
 	memory-region = <&dsp1_memory_region>;
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
@@ -122,3 +122,5 @@
 	status = "okay";
 	memory-region = <&dsp1_memory_region>;
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
@@ -612,3 +612,5 @@
 &gpu {
 	memory-region = <&gpu_memory_region>;
 };
+
+#include "dra7-ipu-common-early-boot.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -437,6 +437,7 @@
 				regulator-name = "vdd_ldo10";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
 				regulator-state-mem {
 					regulator-off-in-suspend;
 				};

diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -437,6 +437,7 @@
 				regulator-name = "vdd_ldo10";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
 				regulator-state-mem {
 					regulator-off-in-suspend;
 				};

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -323,6 +323,7 @@
 	vmmc-supply = <&reg_module_3v3>;
 	vqmmc-supply = <&reg_DCDC3>;
 	non-removable;
+	sdhci-caps-mask = <0x80000000 0x0>;
 };
 
 &iomuxc {

diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -43,7 +43,7 @@
 			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 	assigned-clock-rates = <0>, <100000000>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -69,7 +69,7 @@
 			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 	assigned-clock-rates = <0>, <100000000>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
 	fsl,magic-packet;
 	status = "okay";

diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -135,14 +135,15 @@ restart:
 	orr r11, r11, r13			@ mask all requested interrupts
 	str r11, [r12, #OMAP1510_GPIO_INT_MASK]
 
+	str r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack all requested interrupts
+
 	ands r10, r13, #KEYBRD_CLK_MASK		@ extract keyboard status - set?
 	beq hksw				@ no - try next source
 
 
 	@@@@@@@@@@@@@@@@@@@@@@
 	@ Keyboard clock FIQ mode interrupt handler
 	@ r10 now contains KEYBRD_CLK_MASK, use it
-	str r10, [r12, #OMAP1510_GPIO_INT_STATUS]	@ ack the interrupt
 	bic r11, r11, r10				@ unmask it
 	str r11, [r12, #OMAP1510_GPIO_INT_MASK]
 

diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -73,9 +73,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
 			 * interrupts default to since commit 80ac93c27441
 			 * requires interrupt already acked and unmasked.
 			 */
-			if (irq_chip->irq_ack)
-				irq_chip->irq_ack(d);
-			if (irq_chip->irq_unmask)
+			if (!WARN_ON_ONCE(!irq_chip->irq_unmask))
 				irq_chip->irq_unmask(d);
 		}
 		for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
@@ -131,6 +131,9 @@ static int __init omap4_sram_init(void)
 	struct device_node *np;
 	struct gen_pool *sram_pool;
 
+	if (!soc_is_omap44xx() && !soc_is_omap54xx())
+		return 0;
+
 	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
 	if (!np)
 		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
-Original file line number
+Diff line change
@@ Expand Up / @@ -140,3 +140,5 @@ @@
     &vip2 {
     	status = "okay";
     };
+    #include "dra7-ipu-common-early-boot.dtsi"