ENGR00322272-2: video: mxc ldb: remove ldb_di_sel from pixel rate setup

Since commit 0bec461 (ENGR00318063-8: ARM: imx6q: hide buggy
ldb_di_sel from clk API), the mux clock ldb_di_sel becomes unavailable
from the clock tree.  The LDB driver sets up its pixel clock rate with
the help of ldb_di_sel knowledge, and thus causes problem.  The net
result is the LDB pixel clock rate slows down to 50 MHz (50285714) from
the original 64 MHz (64653061) on imx6q.

The patch fixes the problem by removing the ldb_di_sel knowledge from
the clock configuration path and just setting the rate on div_sel[chno]
clock.  The bonus point is that we can use chan.vm.pixelclock directly
instead of calculating the required rate we need to set on
ldb_di_sel_parent.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

drivers/video/mxc/ldb.c

@@ -389,11 +389,10 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh,
 	struct ldb_data *ldb = mxc_dispdrv_getdata(mddh);
 	struct ldb_chan chan;
 	struct device *dev = ldb->dev;
-	struct clk *ldb_di_parent, *ldb_di_sel, *ldb_di_sel_parent;
+	struct clk *ldb_di_parent, *ldb_di_sel_parent;
 	struct clk *other_ldb_di_sel = NULL;
 	struct bus_mux bus_mux;
 	int ret = 0, id = 0, chno, other_chno;
-	unsigned long serial_clk;
 	u32 mux_val;
 
 	ret = find_ldb_chno(ldb, fbi, &chno);
@@ -421,7 +420,7 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh,
 	}
 
 	/*
-	 * ldb_di_sel_parent(plls) -> ldb_di_sel ->
+	 * ldb_di_sel_parent(plls) ->
 	 *
 	 *     -> div_3_5[chno] ->
 	 * -> |                   |-> div_sel[chno] ->
@@ -433,11 +432,8 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh,
 	ldb_di_parent = ldb->spl_mode ? ldb->div_3_5_clk[chno] :
 			ldb->div_7_clk[chno];
 	clk_set_parent(ldb->div_sel_clk[chno], ldb_di_parent);
-	ldb_di_sel = clk_get_parent(ldb_di_parent);
-	ldb_di_sel_parent = clk_get_parent(ldb_di_sel);
-	serial_clk = ldb->spl_mode ? chan.vm.pixelclock * 7 / 2 :
-			chan.vm.pixelclock * 7;
-	clk_set_rate(ldb_di_sel_parent, serial_clk);
+	ldb_di_sel_parent = clk_get_parent(ldb_di_parent);
+	clk_set_rate(ldb->div_sel_clk[chno], chan.vm.pixelclock);
 
 	/*
 	 * split mode or dual mode: