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Security-RISC
Security-RISC PublicProof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
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browser-cpu-fingerprinting
browser-cpu-fingerprinting PublicThis repository contains the code for our paper "Browser-based CPU Fingerprinting".
Repositories
- xs-observations Public
Code for our 2023 IEEE S&P Paper "The Leaky Web: Automated Discovery of Cross-Site Information Leaks in Browsers and the Web"
cispa/xs-observations’s past year of commit activity - cascading-spy-sheets Public
This repository contains the artifact for our paper "Cascading Spy Sheets: Exploiting the Complexity of Modern CSS for Email and Browser Fingerprinting" published at NDSS 2025.
cispa/cascading-spy-sheets’s past year of commit activity - Security-RISC Public
Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
cispa/Security-RISC’s past year of commit activity - CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet Public
Vivado 2023.2 project built around the CVA6 RISC-V CPU and a software stack including u-boot and embedded linux.
cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet’s past year of commit activity - cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cispa/cva6’s past year of commit activity
