Fast start/restart with clean shutdown to lower power but powered on …

…mode.

cgminer.c

@@ -4460,9 +4460,9 @@ static void __kill_work(void)
 	}
 
 	/* Give the threads a chance to shut down gracefully */
-	cg_completion_timeout(&wait_mining, NULL, 3000);
+	cg_completion_timeout(&wait_mining, NULL, 5000);
 	/* Kill the threads and wait for them to return if not */
-	cg_completion_timeout(&kill_mining, NULL, 3000);
+	cg_completion_timeout(&kill_mining, NULL, 5000);
 
 	/* Stop the others */
 	forcelog(LOG_DEBUG, "Killing off API thread");

dm_compat.c

@@ -747,15 +747,14 @@ void mcompat_set_start_en(unsigned char chain_id, int val)
 }
 
 
-void mcompat_set_reset(unsigned char chain_id, int val)
+bool mcompat_set_reset(unsigned char chain_id, int val)
 {
-	if (s_gpio_ops_p->set_reset == NULL)
-	{
+	if (s_gpio_ops_p->set_reset == NULL) {
 		applog(LOG_ERR, "%s not register !", __FUNCTION__);
-		return;
+		return false;
 	}
 
-	s_gpio_ops_p->set_reset(chain_id, val);
+	return s_gpio_ops_p->set_reset(chain_id, val);
 }
 
 void mcompat_set_led(unsigned char chain_id, int val)
@@ -809,14 +808,12 @@ bool mcompat_set_vid_by_step(unsigned char chain_id, int start_vid, int target_v
 		for (i = start_vid + 1; i <= target_vid; ++i) {
 			mcompat_set_vid(chain_id, i);
 			applog(LOG_NOTICE, "set_vid_value_G19: %d", i);
-			cgsleep_ms(500);
 		}
 	} else if (target_vid < start_vid) {
 		// decrease vid step by step
 		for (i = start_vid - 1; i >= target_vid; --i) {
 			mcompat_set_vid(chain_id, i);
 			applog(LOG_NOTICE, "set_vid_value_G19: %d", i);
-			cgsleep_ms(500);
 		}
 	}
 
@@ -1714,39 +1711,39 @@ void zynq_gpio_init(int pin, int dir)
 	return;
 }
 
-void zynq_gpio_write(int pin, int val)
+static bool zynq_gpio_write(int pin, int val)
 {
 	int  fd = 0;
 	ssize_t  write_bytes = 0;
 	char fpath[BUF_MAX] = {'\0'};
+	bool ret = false;
 
 	memset(fpath, 0, sizeof(fpath));
 	sprintf(fpath, SYSFS_GPIO_VAL_STR, pin);
 	fd = open(fpath, O_WRONLY);
-	if (-1 == fd)
-	{
+	if (-1 == fd) {
 		applog(LOG_ERR, "%s,%d: %s.", __FILE__, __LINE__, strerror(errno));
+		goto out;
 	}
 
-	if (0 == val)
-	{
+	if (0 == val) {
 		write_bytes = write(fd, SYSFS_GPIO_VAL_LOW, sizeof(SYSFS_GPIO_VAL_LOW));
-		if (-1 == write_bytes)
-		{
+		if (-1 == write_bytes) {
 			applog(LOG_ERR, "%s,%d: %s.", __FILE__, __LINE__, strerror(errno));
+			goto out_close;
 		}
-	}
-	else
-	{
+	} else {
 		write_bytes = write(fd, SYSFS_GPIO_VAL_HIGH, sizeof(SYSFS_GPIO_VAL_HIGH));
-		if (-1 == write_bytes)
-		{
+		if (-1 == write_bytes) {
 			applog(LOG_ERR, "%s,%d: %s,%s.", __FILE__, __LINE__, fpath, strerror(errno));
+			goto out_close;
 		}
 	}
-
+	ret = true;
+out_close:
 	close(fd);
-	return;
+out:
+	return ret;
 }
 
 int zynq_gpio_read(int pin)
@@ -3125,14 +3122,15 @@ void hub_set_start_en(uint8_t chain_id, int value)
 }
 
 // 1.8v GPIO output
-void hub_set_reset(uint8_t chain_id, int value)
+bool hub_set_reset(uint8_t chain_id, int value)
 {
 	uint32_t reg_val;
 
 	reg_val = Xil_Peripheral_In32(MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG8_OFFSET);
 	Xil_Peripheral_Out32(MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG8_OFFSET, (reg_val & (~(0x1 << (9 + chain_id)))) | ((value & 0x1) << (9 + chain_id)));
 	//reg_val = Xil_Peripheral_In32(XPAR_VID_LED_BUZZER_CTRL_0_S00_AXI_BASEADDR + VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG0_OFFSET + chain_id*4);
 	//Xil_Peripheral_Out32(XPAR_VID_LED_BUZZER_CTRL_0_S00_AXI_BASEADDR + VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG0_OFFSET + chain_id*4, (reg_val & 0xfffdffff) | ((value & 0x1) << 17));
+	return true;
 }
 
 void hub_set_led(uint8_t chain_id, int mode)
@@ -3666,7 +3664,7 @@ void opi_set_start_en(unsigned char chain_id, int val)
 }
 
 
-void opi_set_reset(unsigned char chain_id, int val)
+bool opi_set_reset(unsigned char chain_id, int val)
 {
 	unsigned char tx_buf[MCOMPAT_CONFIG_MAX_CMD_LENGTH];
 
@@ -3675,17 +3673,16 @@ void opi_set_reset(unsigned char chain_id, int val)
 	tx_buf[0] = (val >> 0) & 0xff;
 	tx_buf[1] = (val >> 8) & 0xff;
 
-	if (!opi_send_cmd(chain_id, OPI_SET_RESET, tx_buf, 2))
-	{
+	if (!opi_send_cmd(chain_id, OPI_SET_RESET, tx_buf, 2)) {
 		applog(LOG_WARNING, "%s,%d: %s send fail !", __FILE__, __LINE__, __FUNCTION__);
-		return;
+		return false;
 	}
 
-	if (!opi_poll_rslt(chain_id, OPI_SET_RESET, NULL, 0))
-	{
+	if (!opi_poll_rslt(chain_id, OPI_SET_RESET, NULL, 0)) {
 		applog(LOG_WARNING, "%s,%d: %s poll fail !", __FILE__, __LINE__, __FUNCTION__);
-		return;
+		return false;
 	}
+	return true;
 }
 
 
@@ -4088,9 +4085,9 @@ void spi_set_start_en(unsigned char chain_id, int val)
 	zynq_gpio_write(pin_start_en[chain_id], val);
 }
 
-void spi_set_reset(unsigned char chain_id, int val)
+bool spi_set_reset(unsigned char chain_id, int val)
 {
-	zynq_gpio_write(pin_reset[chain_id], val);
+	return zynq_gpio_write(pin_reset[chain_id], val);
 }
 
 void spi_set_led(unsigned char chain_id, int val)

dm_compat.h

@@ -200,7 +200,7 @@ typedef struct MCOMPAT_GPIO_TAG{
 	//
 	void (*set_start_en)(unsigned char, int);
 	//
-	void (*set_reset)(unsigned char, int);
+	bool (*set_reset)(unsigned char, int);
 	//
 	void (*set_led)(unsigned char, int);
 	//
@@ -397,7 +397,7 @@ extern void mcompat_set_power_en(unsigned char chain_id, int val);
 
 extern void mcompat_set_start_en(unsigned char chain_id, int val);
 
-extern void mcompat_set_reset(unsigned char chain_id, int val);
+extern bool mcompat_set_reset(unsigned char chain_id, int val);
 
 extern void mcompat_set_led(unsigned char chain_id, int val);
 
@@ -533,8 +533,6 @@ extern void zynq_gpio_init(int pin, int dir);
 
 extern void zynq_gpio_exit(int pin);
 
-extern void zynq_gpio_write(int pin, int val);
-
 extern int zynq_gpio_read(int pin);
 
 
@@ -1225,7 +1223,7 @@ void hub_set_power_en(uint8_t chain_id, int value);
 
 void hub_set_start_en(uint8_t chain_id, int value);
 
-void hub_set_reset(uint8_t chain_id, int value);
+bool hub_set_reset(uint8_t chain_id, int value);
 
 void hub_set_led(uint8_t chain_id, int mode);
 
@@ -1427,7 +1425,7 @@ void opi_set_power_en(unsigned char chain_id, int val);
 
 void opi_set_start_en(unsigned char chain_id, int val);
 
-void opi_set_reset(unsigned char chain_id, int val);
+bool opi_set_reset(unsigned char chain_id, int val);
 
 void opi_set_led(unsigned char chain_id, int val);
 
@@ -1470,7 +1468,7 @@ void exit_spi_gpio(int chain_num);
 
 void spi_set_power_en(unsigned char chain_id, int val);
 void spi_set_start_en(unsigned char chain_id, int val);
-void spi_set_reset(unsigned char chain_id, int val);
+bool spi_set_reset(unsigned char chain_id, int val);
 void spi_set_led(unsigned char chain_id, int val);
 bool spi_set_vid(unsigned char chain_id, int vid);
 int spi_get_plug(unsigned char chain_id);

dm_fan_ctrl.c

@@ -25,10 +25,6 @@
  * Macros & Constants
  ******************************************************************************/
 #define FAN_MODE_DEF			FAN_MODE_AUTO		// default fan control mode
-#define FAN_SPEED_MAX			(100)			// max fan speed (%)
-#define FAN_SPEED_MIN			(0)			// min fan speed (%)
-#define FAN_SPEED_DEF			(80)			// default fan speed (%)
-#define FAN_SPEED_PREHEAT		(10)			// preheat fan speed
 
 #define WORK_CYCLE_DEF			(2)			// default time interval between temperature checks
 #define DEV_TMP_CHK_CNT			(3)

dm_fan_ctrl.h

@@ -1,5 +1,6 @@
 /*
  * Copyright 2018 Duan Hao
+ * Copyright 2018 Con Kolivas <kernel@kolivas.org>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
@@ -10,6 +11,11 @@
 #ifndef _DM_FAN_CTRL_H_
 #define _DM_FAN_CTRL_H_
 
+#define FAN_SPEED_MAX			(100)			// max fan speed (%)
+#define FAN_SPEED_MIN			(0)			// min fan speed (%)
+#define FAN_SPEED_DEF			(80)			// default fan speed (%)
+#define FAN_SPEED_PREHEAT		(10)			// preheat fan speed
+
 typedef enum _FAN_MODE
 {
 	FAN_MODE_MANUAL	= 0,				// manual fan control mode

dragonmint_t1.c

@@ -711,8 +711,6 @@ extern struct T1_chain *chain[MAX_CHAIN_NUM];
 extern uint8_t chain_mask;
 extern hardware_version_e g_hwver;
 //int chain_voltage_flag[MAX_CHAIN_NUM];
-int chain_encore_flag[MAX_CHAIN_NUM];
-bool alreadyRetryFull = false;
 
 #if 0
 const unsigned short wCRCTalbeAbs[] =
@@ -824,13 +822,10 @@ bool T1_SetT1PLLClock(struct T1_chain *t1, int pllClkIdx, int chip_id)
 
 	memcpy(temp_reg, default_reg[pllClkIdx], REG_LENGTH);
 
-	/* Sleep 120ms since the LAST time we set pll */
-	cgsleep_ms_r(&t1->cgt_pll, 10);
 	if (!mcompat_cmd_write_register(cid, chip_id, temp_reg, REG_LENGTH)) {
 		applog(LOG_WARNING, "Failed to set PLL Lv.%d on T1 %d in T1_SetT1PLLClock", pllClkIdx, cid);
 		return false;
 	}
-	cgsleep_prepare_r(&t1->cgt_pll);
 	if (chip_id) {
 		applog(LOG_NOTICE, "T1 %d chip %d PLL set to %d %d MHz", cid, chip_id,
 		       pllClkIdx, PLL_Clk_12Mhz[pllClkIdx].speedMHz);
@@ -1323,28 +1318,6 @@ void power_down_all_chain(void)
 	}
 }
 
-void dragonmint_miner_encore_save(void)
-{
-	FILE* fd;
-	int i;
-
-	for (i = 0; i < MAX_CHAIN_NUM; i++) {
-		char fileName[128];
-
-		if (chain_plug[i] != 1 || !chain_encore_flag[i])
-			continue;
-
-		sprintf(fileName, "%s%d.log", LOG_FILE_ENCORE_PREFIX, i);
-		fd = fopen(fileName, "w+");
-		if (fd == NULL){
-			applog(LOG_ERR, "Open to write miner encore retry file failed!");
-			return;
-		}
-		fprintf(fd, "%d", chain_encore_flag[i]);
-		fclose(fd);
-	}
-}
-
 void write_miner_ageing_status(uint32_t statusCode)
 {
 	FILE* fd;
@@ -1364,16 +1337,14 @@ void write_miner_ageing_status(uint32_t statusCode)
 
 bool t1_set_pll(struct T1_chain *t1, int chip_id, int target_pll)
 {
-	int i, start_pll = t1->pll, chain_id = t1->chain_id;
+	int i, start_pll = t1->pll;
 	uint8_t reg[REG_LENGTH] = {0};
 
 	if (target_pll > start_pll) {
 		// increase pll step by step
 		for (i = start_pll; i <= target_pll; i++) {
 			memcpy(reg, default_reg[i], REG_LENGTH);
 			if (!T1_SetT1PLLClock(t1, i, chip_id)) {
-				mcompat_chain_power_down(chain_id);
-				chain_flag[chain_id] = 0;
 				applog(LOG_WARNING, "set default PLL fail");
 				write_miner_ageing_status(AGEING_CONFIG_PLL_FAILED);
 				return false;
@@ -1388,8 +1359,6 @@ bool t1_set_pll(struct T1_chain *t1, int chip_id, int target_pll)
 		for (i = start_pll; i >= target_pll; i--) {
 			memcpy(reg, default_reg[i], REG_LENGTH);
 			if (!T1_SetT1PLLClock(t1, i, chip_id)) {
-				mcompat_chain_power_down(chain_id);
-				chain_flag[chain_id] = 0;
 				applog(LOG_WARNING, "set default PLL fail");
 				write_miner_ageing_status(AGEING_CONFIG_PLL_FAILED);
 				return false;
@@ -1406,28 +1375,3 @@ bool t1_set_pll(struct T1_chain *t1, int chip_id, int target_pll)
 
 	return true;
 }
-
-void dragonmint_miner_get_encore_flag(int chain_id)
-{
-	FILE* fd;
-	int retryCnt;
-	char fileName[128];
-
-	sprintf(fileName, "%s%d.log", LOG_FILE_ENCORE_PREFIX, chain_id);
-	if ((access(fileName, F_OK)) != -1) {
-		applog(LOG_ERR, "Miner init encore retry file already exists!");
-		fd = fopen(fileName, "r+");
-		if (fd == NULL) {
-			applog(LOG_ERR, "Open miner init encore retry file failed!");
-			return;
-		}
-		if (fscanf(fd, "%d", &retryCnt) < 1)
-			applog(LOG_ERR, "Fscanf of miner init encore retry file failed!");
-		else {
-			applog(LOG_INFO, "Miner init encore retry count is %d!", retryCnt);
-			chain_encore_flag[chain_id] = retryCnt;
-		}
-		fclose(fd);
-	}
-	return;
-}

dragonmint_t1.h

@@ -48,13 +48,7 @@
 #define DRAGONMINT_MINER_TYPE_FILE				"/tmp/type"
 #define DRAGONMINT_HARDWARE_VERSION_FILE			"/tmp/hwver"
 #define DRAGONMINT_CHIP_NUM_FILE				"/tmp/chip_nums"
-#define DRAGONMINT_MINER_RETRY_FILE				"/tmp/retryCnt"
-#define DRAGONMINT_CHAIN_ABNORMAL_FILE				"/tmp/chainretryCnt"
 #define MINER_AGEING_STATUS_FILE				"/tmp/ageingStatus"
-#define LOG_FILE_ENCORE_PREFIX					"/tmp/encore_flag_chain"
-#define DRAGONMINT_MINER_RETRY_COUNT				(2)
-#define DRAGONMINT_CHAIN_ABNORMAL_RETRY_CNT			(3)
-#define DRAGONMINT_MINER_ENCORE_RETRY_COUNT			(3)
 
 #define T1_PLL(prediv,fbdiv,postdiv) ((prediv<<(89-64))|fbdiv<<(80-64)|0b010<<(77-64)|postdiv<<(70-64))
 
@@ -178,8 +172,6 @@ struct T1_chain {
 	double pllhwerr[T1_PLL_TUNE_RANGE]; // hwerr vs pll level
 	int pllvid[T1_PLL_TUNE_RANGE]; // Associated VID per pll
 
-	cgtimer_t cgt_pll; // Last time we set pll
-
 	bool VidOptimal; // We've stopped tuning voltage
 	bool pllOptimal; // We've stopped tuning frequency
 	bool sampling; // Results are valid for tuning
@@ -233,11 +225,9 @@ uint32_t dragonmint_get_chipnum(void);
 
 void chain_all_exit(void);
 void power_down_all_chain(void);
-void dragonmint_miner_encore_save(void);
 void write_miner_ageing_status(uint32_t statusCode);
 int dragonmint_get_voltage_stats(struct T1_chain *t1, dragonmint_reg_ctrl_t *s_reg_ctrl);
 
-extern void dragonmint_miner_get_encore_flag(int chain_id);
 bool t1_set_pll(struct T1_chain *t1, int chip_id, int target_pll);
 
 bool T1_SetT1PLLClock(struct T1_chain *t1,int pllClkIdx, int chip_id);