Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

build: Bump tock-registers from 0.8.1 to 0.9.0 #292

Merged
merged 2 commits into from
Oct 30, 2023
+18 −8
Merged

build: Bump tock-registers from 0.8.1 to 0.9.0 #292

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
ca8cf3e
aarch64: Use aarch64_cpu::registers traits
retrage Oct 28, 2023
600ec26
build: Bump tock-registers from 0.8.1 to 0.9.0
dependabot[bot] Oct 28, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 8 additions & 2 deletions Cargo.lock
View file
Open in desktop

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

2 changes: 1 addition & 1 deletion Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ r-efi = { version = "4.3.0", features = ["efiapi"] }
linked_list_allocator = "0.10.4"

[target.'cfg(target_arch = "aarch64")'.dependencies]
tock-registers = "0.8.1"
tock-registers = "0.9.0"
aarch64-cpu = "9.4.0"
fdt = "0.1.5"
chrono = { version = "0.4", default-features = false }
Expand Down
11 changes: 8 additions & 3 deletions src/arch/aarch64/paging.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,10 @@

use core::ops::RangeInclusive;

use aarch64_cpu::{asm::barrier, registers::*};
use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
use aarch64_cpu::{
asm::barrier,
registers::{Readable, Writeable, *},
};

use self::interface::Mmu;

Expand Down Expand Up @@ -287,7 +289,10 @@ impl interface::Mmu for MemoryManagementUnit {
barrier::isb(barrier::SY);

// Enable the MMU and turn on data and instruction caching.
SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
SCTLR_EL1.modify_no_read(
SCTLR_EL1.extract(),
SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable,
);

// Force MMU init to complete before next instruction.
barrier::isb(barrier::SY);
Expand Down
3 changes: 1 addition & 2 deletions src/arch/aarch64/simd.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,7 @@
// Copyright (C) 2023 Akira Moroo

use aarch64_cpu::registers::*;
use tock_registers::interfaces::ReadWriteable;

pub fn setup_simd() {
CPACR_EL1.modify(CPACR_EL1::FPEN::TrapNothing);
CPACR_EL1.modify_no_read(CPACR_EL1.extract(), CPACR_EL1::FPEN::TrapNothing);
}
Loading