Changed monitor sample to prepone region of correct clock edge

cocotb · Sep 21, 2021 · 2aa3a1f · 2aa3a1f
1 parent a3e22f7
commit 2aa3a1f
Showing 1 changed file with 0 additions and 4 deletions.
diff --git a/src/cocotb_bus/monitors/avalon.py b/src/cocotb_bus/monitors/avalon.py
@@ -49,7 +49,6 @@ async def _monitor_recv(self):
 
         # Avoid spurious object creation by recycling
         clkedge = RisingEdge(self.clock)
-        rdonly = ReadOnly()
 
         def valid():
             if hasattr(self.bus, "ready"):
@@ -59,7 +58,6 @@ def valid():
         # NB could await on valid here more efficiently?
         while True:
             await clkedge
-            await rdonly
             if valid():
                 vec = self.bus.data.value
                 vec.big_endian = self.config["firstSymbolInHighOrderBits"]
@@ -130,7 +128,6 @@ async def _monitor_recv(self):
 
         # Avoid spurious object creation by recycling
         clkedge = RisingEdge(self.clock)
-        rdonly = ReadOnly()
         pkt = b""
         in_pkt = False
         invalid_cyclecount = 0
@@ -143,7 +140,6 @@ def valid():
 
         while True:
             await clkedge
-            await rdonly
 
             if self.in_reset:
                 continue