Merge pull request torvalds#353 from analogdevicesinc/master-xilinx-2…

…018.3

master: update with xilinx-v2018.3 release tag

The testing has been finalized on the HDL side.
The code from  xilinx-v2018.3 release tag has also been validated.

The only major highlight for this change (other than Xilinx patches) is this patch 1f47ad4  ("serial: uartlite: fix null dereference on probe error path") which was also sent to Xilinx and applied to their master.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>

Documentation/devicetree/bindings/clock/silabs,si5324.txt

@@ -0,0 +1,78 @@
+Binding for Silicon Labs si5324, si5328 and si5319 programmable
+I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1].
+The si5324 is programmable i2c low-bandwidth, jitter-attenuating, precision
+clock multiplier with up to 2 output clocks. The internal structure can be
+found in [2].
+The internal pin structure of si5328 and si5319 can be found in [3].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si5324 Data Sheet
+ http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
+[3] Si53xx Reference Manual
+ http://www.silabs.com/Support%20Documents/TechnicalDocs/
+ Si53xxReferenceManual.pdf
+
+==I2C device node==
+
+Required properties:
+- compatible: should be one of
+ "silabs,si5324"
+ "silabs,si5319"
+ "silabs,si5328"
+- reg: i2c device address.
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: from common clock binding; list of parent clock
+ handles, clock name should be one of
+ "xtal"
+ "clkin1"
+ "clkin2"
+- #address-cells: shall be set to 1.
+- #size-cells: shall be set to 0.
+
+Optional properties:
+- silabs,pll-source: pair of (number, source) for each pll. Allows
+ to overwrite clock source of pll.
+
+==Child nodes==
+
+Each of the clock outputs can be overwritten individually by
+using a child node to the I2C device node. If a child node for a clock
+output is not set, the eeprom configuration is not overwritten.
+
+Required child node properties:
+- reg: number of clock output.
+- clock-frequency: default output frequency at power on
+
+Optional child node properties:
+- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
+
+Example:
+Following example describes the ZCU102 board with hdmi design which
+uses si5319 as clock generator. XTAL is hard-wired on the board to act
+as input clock with a frequency of 114.285MHz.
+
+refhdmi: refhdmi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <114285000>;
+};
+
+/* Si5319 i2c clock generator */
+si5319: clock-generator@68 {
+ status = "okay";
+ compatible = "silabs,si5319";
+ reg = <0x68>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+
+ clk0 {
+ reg = <0>;
+ clock-frequency = <27000000>;
+ };
+};

Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

@@ -35,10 +35,14 @@ The following strings are optional parameters to the 'clock-names' property in
 order to provide an optional (E)MIO clock source.
  - swdt0_ext_clk
  - swdt1_ext_clk
- - gem0_emio_clk
- - gem1_emio_clk
- - gem2_emio_clk
- - gem3_emio_clk
+ - gem0_tx_ext
+ - gem1_tx_ext
+ - gem2_tx_ext
+ - gem3_tx_ext
+ - gem0_rx_ext
+ - gem1_rx_ext
+ - gem2_rx_ext
+ - gem3_rx_ext
  - mio_clk_XX # with XX = 00..77
  - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
 
@@ -94,14 +98,14 @@ Clock ID: Output clock name:
 42 iou_switch
 43 gem_tsu_ref
 44 gem_tsu
-45 gem0_ref
-46 gem1_ref
-47 gem2_ref
-48 gem3_ref
-49 gem0_tx
-50 gem1_tx
-51 gem2_tx
-52 gem3_tx
+45 gem0_tx
+46 gem1_tx
+47 gem2_tx
+48 gem3_tx
+49 gem0_rx
+50 gem1_rx
+51 gem2_rx
+52 gem3_rx
 53 qspi_ref
 54 sdio0_ref
 55 sdio1_ref
@@ -152,6 +156,15 @@ Clock ID: Output clock name:
 100 vpll_post_src
 101 can0_mio
 102 can1_mio
+103 acpu_full
+104 gem0_ref
+105 gem1_ref
+106 gem2_ref
+107 gem3_ref
+108 gem0_ref_ung
+109 gem1_ref_ung
+110 gem2_ref_ung
+111 gem3_ref_ung
 
 Example:
 

Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt

@@ -0,0 +1,12 @@
+Xilinx ZynqMP AES hw acceleration support
+
+The ZynqMP PS-AES hw accelerator is used to encrypt/decrypt
+the given user data.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-aes"
+
+Example:
+ zynqmp_aes {
+ compatible = "xlnx,zynqmp-aes";
+ };

Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt

@@ -11,10 +11,13 @@ Required properties:
  external device. In the display controller port nodes, topology
  for entire pipeline should be described using the DT bindings defined in
  Documentation/devicetree/bindings/graph.txt.
+ Minimum one port is required. At max, 2 ports are present.
+ The reg index for AXI4 stream port is 0 and for ancillary data is 1.
 
 Optional properties:
  - xlnx,vpss: vpss phandle
  This handle is required only when VPSS is connected to SDI as bridge.
+ - xlnx,tx-insert-c-str-st352: Insert ST352 payload in Chroma stream.
 
 Example:
 
@@ -26,10 +29,21 @@ Example:
  #address-cells = <1>;
  #size-cells = <0>;
  xlnx,vpss = <&v_proc_ss_0>;
- encoder_sdi_port: port@0 {
- reg = <0>;
- sdi_encoder: endpoint {
- remote-endpoint = <&xyz_port>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ encoder_sdi_port: port@0 {
+ reg = <0>;
+ sdi_encoder: endpoint {
+ remote-endpoint = <&pl_disp_crtc>;
+ };
+ };
+
+ sdi_audio_port: port@1 {
+ reg = <1>;
+ sdi_audio_sink_port: endpoint {
+ remote-endpoint = <&sditx_audio_embed_src_port>;
+ };
  };
  };
  };

Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt

@@ -46,6 +46,10 @@ Optional Properties Common to both FB Read and FB Write for v2.1:
 - xlnx,fid : Field ID enabled for interlaced video support.
  Can be absent for progressive video.
 
+Optional properties:
+- xlnx,max-height : Maximum number of lines.
+- xlnx,max-width : Maximum number of pixels in a line.
+
 VIDEO FORMATS
 The following table describes the legal string values to be used for
 the xlnx,vid-formats property. To the left is the string value and the

Documentation/devicetree/bindings/fpga/xilinx-zynqmp-fpga-mgr.txt

@@ -2,8 +2,12 @@ Xilinx Zynqmp FPGA Manager
 
 Required properties:
 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
+- clocks: phandle for clocks required operation
+- clock-names: name for the clock, should be "ref_clk"
 
 Example:
  pcap: pcap@00 {
  compatible = "xlnx,zynqmp-pcap-fpga";
+ clocks = <&clkc 41>;
+ clock-names = "ref_clk";
  };

Documentation/devicetree/bindings/fpga/xlnx,zynq-afi-fpga.txt

@@ -0,0 +1,19 @@
+Xilinx Zynq AFI interface Manager
+
+The Zynq Processing System core provides access from PL masters to PS
+internal peripherals, and memory through AXI FIFO interface
+(AFI) interfaces.
+
+Required properties:
+-compatible: Should contain "xlnx,zynq-afi-fpga"
+-reg: Physical base address and size of the controller's register area.
+-xlnx,afi-buswidth : Size of the afi bus width.
+ 0: 64-bit AXI data width,
+ 1: 32-bit AXI data width,
+
+Example:
+afi0: afi0 {
+ compatible = "xlnx,zynq-afi-fpga";
+ reg = <0xf8008000 0x1000>;
+ xlnx,afi-buswidth = <1>;
+};

Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

@@ -59,6 +59,10 @@ Required properties:
 - data-lanes: The number of data lanes through which CSI2 Rx Subsystem is
  connected to the camera sensor as per video-interfaces.txt
 
+Optional Properties
+
+- xlnx,en-vcx: When present, the max number of virtual channels can be 16 else 4.
+
 Example:
 
  csiss_1: csiss@a0020000 {

Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt

@@ -0,0 +1,25 @@
+Xilinx Video IP MEM2MEM Pipeline (XVIM2M)
+----------------------------------------
+
+Xilinx video IP mem2mem pipeline processes DMA transfers to achieve memory
+copy from one physical memory to other. The data is copied by employing two
+DMA transfers memory to device and device to memory transactions one after
+the other. The DT node of the XVIM2M represents as a top level node of the
+pipeline and defines mappings between DMAs.
+
+Required properties:
+
+- compatible: Must be "xlnx,mem2mem".
+
+- dmas, dma-names: List of two DMA specifier and identifier strings (as
+ defined in Documentation/devicetree/bindings/dma/dma.txt) per port.
+ Identifier string of one DMA channel should be "tx" and other should be
+ "rx".
+
+Example:
+
+ video_m2m {
+ compatible = "xlnx,mem2mem";
+ dmas = <&dma_1 0>, <&dma_2 0>;
+ dma-names = "tx", "rx";
+ };

Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt

@@ -23,6 +23,11 @@ Required properties:
 
 - xlnx,line-rate: The maximum mode supported by the design.
 
+- clocks: Input clock specifier. Refer to common clock bindings.
+
+- clock-names: List of input clocks.
+ Required elements: "s_axi_aclk", "sdi_rx_clk", "video_out_clk"
+
 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
  The SDI Rx subsystem has one port configured as output port.
 
@@ -40,6 +45,8 @@ Example:
  xlnx,include-edh = "true";
  xlnx,include-vid-over-axi = "true";
  xlnx,line-rate = "12G_SDI_8DS";
+ clocks = <&clk_1>, <&si570_1>, <&clk_2>;
+ clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk";
 
  ports {
  #address-cells = <1>;