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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT | ||
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#include "qcom-ipq4019.dtsi" | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/input/input.h> | ||
#include <dt-bindings/soc/qcom,tcsr.h> | ||
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/ { | ||
model = "YYeTs LE1"; | ||
compatible = "yyets,le1"; | ||
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aliases { | ||
led-boot = &led_usb; | ||
led-failsafe = &led_usb; | ||
led-upgrade = &led_usb; | ||
}; | ||
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keys { | ||
compatible = "gpio-keys"; | ||
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reset { | ||
label = "reset"; | ||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; | ||
linux,code = <KEY_RESTART>; | ||
}; | ||
}; | ||
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leds { | ||
compatible = "gpio-leds"; | ||
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led_usb: usb { | ||
label = "green:usb"; | ||
gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; | ||
linux,default-trigger = "usbport"; | ||
trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>; | ||
}; | ||
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wlan2g { | ||
label = "green:wlan2g"; | ||
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; | ||
linux,default-trigger = "phy0tpt"; | ||
}; | ||
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wlan5g { | ||
label = "green:wlan5g"; | ||
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; | ||
linux,default-trigger = "phy1tpt"; | ||
}; | ||
}; | ||
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soc { | ||
mdio@90000 { | ||
status = "okay"; | ||
pinctrl-0 = <&mdio_pins>; | ||
pinctrl-names = "default"; | ||
}; | ||
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ess-psgmii@98000 { | ||
status = "okay"; | ||
}; | ||
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tcsr@1949000 { | ||
compatible = "qcom,tcsr"; | ||
reg = <0x1949000 0x100>; | ||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; | ||
}; | ||
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tcsr@194b000 { | ||
compatible = "qcom,tcsr"; | ||
reg = <0x194b000 0x100>; | ||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>; | ||
}; | ||
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ess_tcsr@1953000 { | ||
compatible = "qcom,tcsr"; | ||
reg = <0x1953000 0x1000>; | ||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>; | ||
}; | ||
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tcsr@1957000 { | ||
compatible = "qcom,tcsr"; | ||
reg = <0x1957000 0x100>; | ||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; | ||
}; | ||
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ess-switch@c000000 { | ||
status = "okay"; | ||
}; | ||
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edma@c080000 { | ||
status = "okay"; | ||
}; | ||
}; | ||
}; | ||
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&blsp_dma { | ||
status = "okay"; | ||
}; | ||
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&blsp1_spi1 { | ||
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; | ||
pinctrl-0 = <&spi_0_pins>; | ||
pinctrl-names = "default"; | ||
status = "okay"; | ||
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flash@0 { | ||
compatible = "jedec,spi-nor"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
reg = <0>; | ||
spi-max-frequency = <24000000>; | ||
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partitions { | ||
compatible = "fixed-partitions"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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partition@0 { | ||
label = "SBL1"; | ||
reg = <0x0 0x40000>; | ||
read-only; | ||
}; | ||
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partition@40000 { | ||
label = "MIBIB"; | ||
reg = <0x40000 0x20000>; | ||
read-only; | ||
}; | ||
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partition@60000 { | ||
label = "QSEE"; | ||
reg = <0x60000 0x60000>; | ||
read-only; | ||
}; | ||
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partition@c0000 { | ||
label = "CDT"; | ||
reg = <0xc0000 0x10000>; | ||
read-only; | ||
}; | ||
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partition@d0000 { | ||
label = "DDRPARAMS"; | ||
reg = <0xd0000 0x10000>; | ||
read-only; | ||
}; | ||
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partition@e0000 { | ||
label = "APPSBLENV"; | ||
reg = <0xe0000 0x10000>; | ||
read-only; | ||
}; | ||
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partition@f0000 { | ||
label = "APPSBL"; | ||
reg = <0xf0000 0x80000>; | ||
read-only; | ||
}; | ||
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partition@170000 { | ||
label = "ART"; | ||
reg = <0x170000 0x10000>; | ||
read-only; | ||
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compatible = "nvmem-cells"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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precal_art_1000: precal@1000 { | ||
reg = <0x1000 0x2f20>; | ||
}; | ||
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precal_art_5000: precal@5000 { | ||
reg = <0x5000 0x2f20>; | ||
}; | ||
}; | ||
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partition@180000 { | ||
compatible = "denx,fit"; | ||
label = "firmware"; | ||
reg = <0x180000 0x1e80000>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
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&blsp1_uart1 { | ||
pinctrl-0 = <&serial_pins>; | ||
pinctrl-names = "default"; | ||
status = "okay"; | ||
}; | ||
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&cryptobam { | ||
status = "okay"; | ||
}; | ||
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&crypto { | ||
status = "okay"; | ||
}; | ||
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&prng { | ||
status = "okay"; | ||
}; | ||
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&tlmm { | ||
mdio_pins: mdio_pinmux { | ||
mux_1 { | ||
pins = "gpio6"; | ||
function = "mdio"; | ||
bias-pull-up; | ||
}; | ||
mux_2 { | ||
pins = "gpio7"; | ||
function = "mdc"; | ||
bias-pull-up; | ||
}; | ||
}; | ||
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serial_pins: serial_pinmux { | ||
mux { | ||
pins = "gpio16", "gpio17"; | ||
function = "blsp_uart0"; | ||
bias-disable; | ||
}; | ||
}; | ||
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spi_0_pins: spi_0_pinmux { | ||
pinmux { | ||
function = "blsp_spi0"; | ||
pins = "gpio13", "gpio14", "gpio15"; | ||
drive-strength = <12>; | ||
bias-disable; | ||
}; | ||
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pinmux_cs { | ||
function = "gpio"; | ||
pins = "gpio12"; | ||
drive-strength = <2>; | ||
bias-disable; | ||
output-high; | ||
}; | ||
}; | ||
}; | ||
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&usb2 { | ||
status = "okay"; | ||
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dwc3@6000000 { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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usb2_port1: port@1 { | ||
reg = <1>; | ||
#trigger-source-cells = <0>; | ||
}; | ||
}; | ||
}; | ||
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&usb2_hs_phy { | ||
status = "okay"; | ||
}; | ||
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&usb3 { | ||
status = "okay"; | ||
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dwc3@8a00000 { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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usb3_port1: port@1 { | ||
reg = <1>; | ||
#trigger-source-cells = <0>; | ||
}; | ||
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usb3_port2: port@2 { | ||
reg = <2>; | ||
#trigger-source-cells = <0>; | ||
}; | ||
}; | ||
}; | ||
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&usb3_hs_phy { | ||
status = "okay"; | ||
}; | ||
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&usb3_ss_phy { | ||
status = "okay"; | ||
}; | ||
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&watchdog { | ||
status = "okay"; | ||
}; | ||
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&wifi0 { | ||
status = "okay"; | ||
nvmem-cells = <&precal_art_1000>; | ||
nvmem-cell-names = "pre-calibration"; | ||
qcom,ath10k-calibration-variant = "YYeTs-LE1"; | ||
}; | ||
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&wifi1 { | ||
status = "okay"; | ||
nvmem-cells = <&precal_art_5000>; | ||
nvmem-cell-names = "pre-calibration"; | ||
qcom,ath10k-calibration-variant = "YYeTs-LE1"; | ||
}; |
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