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MIPS: tlbex: Avoid placing software PTE bits in Entry* PFN fields
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Commit 748e787 ("MIPS: Optimize TLB refill for RI/XI
configurations.") stopped explicitly clearing the bits used by software
in PTEs by making use of a rotate instruction that rotates them into the
fill bits of the Entry{Lo,Hi} register. This can only work if there are
actually enough fill bits in the register to cover the software
maintained bits, otherwise we end up writing those bits into the upper
bits of the PFN or PFNX field of the Entry{Lo,Hi} register.

Fix this by detecting the number of fill bits present in the
Entry{Lo,Hi} registers & explicitly clearing the software bits where
necessary.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/11218/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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paulburton authored and ralfbaechle committed Nov 11, 2015
1 parent c695672 commit 00bf1c6
Showing 1 changed file with 45 additions and 2 deletions.
47 changes: 45 additions & 2 deletions arch/mips/mm/tlbex.c
Original file line number Diff line number Diff line change
Expand Up @@ -311,6 +311,7 @@ static struct uasm_label labels[128];
static struct uasm_reloc relocs[128];

static int check_for_high_segbits;
static bool fill_includes_sw_bits;

static unsigned int kscratch_used_mask;

Expand Down Expand Up @@ -630,8 +631,14 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
unsigned int reg)
{
if (cpu_has_rixi) {
UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
if (cpu_has_rixi && _PAGE_NO_EXEC) {
if (fill_includes_sw_bits) {
UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
} else {
UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
UASM_i_ROTR(p, reg, reg,
ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
}
} else {
#ifdef CONFIG_PHYS_ADDR_T_64BIT
uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
Expand Down Expand Up @@ -2338,6 +2345,41 @@ static void config_xpa_params(void)
#endif
}

static void check_pabits(void)
{
unsigned long entry;
unsigned pabits, fillbits;

if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
/*
* We'll only be making use of the fact that we can rotate bits
* into the fill if the CPU supports RIXI, so don't bother
* probing this for CPUs which don't.
*/
return;
}

write_c0_entrylo0(~0ul);
back_to_back_c0_hazard();
entry = read_c0_entrylo0();

/* clear all non-PFN bits */
entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);

/* find a lower bound on PABITS, and upper bound on fill bits */
pabits = fls_long(entry) + 6;
fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);

/* minus the RI & XI bits */
fillbits -= min_t(unsigned, fillbits, 2);

if (fillbits >= ilog2(_PAGE_NO_EXEC))
fill_includes_sw_bits = true;

pr_debug("Entry* registers contain %u fill bits\n", fillbits);
}

void build_tlb_refill_handler(void)
{
/*
Expand All @@ -2348,6 +2390,7 @@ void build_tlb_refill_handler(void)
static int run_once = 0;

output_pgtable_bits_defines();
check_pabits();

#ifdef CONFIG_64BIT
check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
Expand Down

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