PortBundles cannot contain lists #125
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dmlockhart
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Feb 17, 2015
Some parameterizable generated code depends on the ability to slice one-bit wires. For example, accel/mvmult/MatrixVecLaneRTL.py contains a wrapper for a multiply operation we use to enable register retiming for a synthesized multiplier. It has a parametrizable number of register stages, these registers can be enabled individually using the nbit s.enables input port. The bitwidth of s.enables is set by the nstages parameter, and a loop in the posedge_clk block is used with slicing to read each enable bit. This works fine if nstages is > 1 (wire [nstages-1:0] enable), but if nstages is 1 the lack of the [0:0] prevents the wire from being sliced. When we had [0:0] it worked as expected. I tried fixing the code to work around this limitation, but PortBundles currently do not support lists of ports (opened as issue #125).
dmlockhart
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Aug 26, 2015
Some parameterizable generated code depends on the ability to slice one-bit wires. For example, accel/mvmult/MatrixVecLaneRTL.py contains a wrapper for a multiply operation we use to enable register retiming for a synthesized multiplier. It has a parametrizable number of register stages, these registers can be enabled individually using the nbit s.enables input port. The bitwidth of s.enables is set by the nstages parameter, and a loop in the posedge_clk block is used with slicing to read each enable bit. This works fine if nstages is > 1 (wire [nstages-1:0] enable), but if nstages is 1 the lack of the [0:0] prevents the wire from being sliced. When we had [0:0] it worked as expected. I tried fixing the code to work around this limitation, but PortBundles currently do not support lists of ports (opened as issue #125).
dmlockhart
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Aug 26, 2015
Some parameterizable generated code depends on the ability to slice one-bit wires. For example, accel/mvmult/MatrixVecLaneRTL.py contains a wrapper for a multiply operation we use to enable register retiming for a synthesized multiplier. It has a parametrizable number of register stages, these registers can be enabled individually using the nbit s.enables input port. The bitwidth of s.enables is set by the nstages parameter, and a loop in the posedge_clk block is used with slicing to read each enable bit. This works fine if nstages is > 1 (wire [nstages-1:0] enable), but if nstages is 1 the lack of the [0:0] prevents the wire from being sliced. When we had [0:0] it worked as expected. I tried fixing the code to work around this limitation, but PortBundles currently do not support lists of ports (opened as issue #125).
dmlockhart
added a commit
that referenced
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Aug 31, 2015
Some parameterizable generated code depends on the ability to slice one-bit wires. For example, accel/mvmult/MatrixVecLaneRTL.py contains a wrapper for a multiply operation we use to enable register retiming for a synthesized multiplier. It has a parametrizable number of register stages, these registers can be enabled individually using the nbit s.enables input port. The bitwidth of s.enables is set by the nstages parameter, and a loop in the posedge_clk block is used with slicing to read each enable bit. This works fine if nstages is > 1 (wire [nstages-1:0] enable), but if nstages is 1 the lack of the [0:0] prevents the wire from being sliced. When we had [0:0] it worked as expected. I tried fixing the code to work around this limitation, but PortBundles currently do not support lists of ports (opened as issue #125).
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