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[pclib/rtl] added special case to register file for single read port #163

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[pclib/rtl] added special case to register file for single read port #163

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47 changes: 39 additions & 8 deletions pclib/rtl/RegisterFile.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,12 @@ def __init__( s, dtype = Bits(32), nregs = 32, rd_ports = 1, wr_ports = 1,
const_zero=False ):

addr_nbits = clog2( nregs )

s.rd_addr = [ InPort ( addr_nbits ) for _ in range(rd_ports) ]
s.rd_data = [ OutPort( dtype ) for _ in range(rd_ports) ]

if rd_ports == 1:
s.rd_addr = InPort( addr_nbits )
s.rd_data = InPort( dtype )
else:
s.rd_addr = [ InPort ( addr_nbits ) for _ in range(rd_ports) ]
s.rd_data = [ OutPort( dtype ) for _ in range(rd_ports) ]
if wr_ports == 1:
s.wr_addr = InPort( addr_nbits )
s.wr_data = InPort( dtype )
Expand All @@ -28,13 +30,28 @@ def __init__( s, dtype = Bits(32), nregs = 32, rd_ports = 1, wr_ports = 1,

s.regs = [ Wire( dtype ) for _ in range( nregs ) ]


# Select read logic depending on if this register file should have
# a constant zero register or not, or single port!

#-------------------------------------------------------------------
# Combinational read logic
# Combination read logic, single read port, constant zero
#-------------------------------------------------------------------
if const_zero and rd_ports == 1:

# constant zero

if const_zero:
@s.combinational
def comb_logic():
for i in range( rd_ports ):
assert s.rd_addr < nregs
if s.rd_addr == 0:
s.rd_data.value = 0
else:
s.rd_data.value = s.regs[ s.rd_addr ]

#-------------------------------------------------------------------
# Combination read logic, multiple read port, constant zero
#-------------------------------------------------------------------
elif const_zero:

@s.combinational
def comb_logic():
Expand All @@ -44,7 +61,21 @@ def comb_logic():
s.rd_data[i].value = 0
else:
s.rd_data[i].value = s.regs[ s.rd_addr[i] ]

#-------------------------------------------------------------------
# Combination read logic, single read port
#-------------------------------------------------------------------
elif rd_ports == 1:

@s.combinational
def comb_logic():
for i in range( rd_ports ):
assert s.rd_addr < nregs
s.rd_data.value = s.regs[ s.rd_addr ]

#-------------------------------------------------------------------
# Combination read logic, multiple read port
#-------------------------------------------------------------------
else:

@s.combinational
Expand Down
8 changes: 4 additions & 4 deletions pclib/rtl/RegisterFile_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -44,14 +44,14 @@ def test_regfile_1R1W( dump_vcd, test_verilog ):
# Define functions mapping the test vector to ports in model

def tv_in( model, test_vector ):
model.rd_addr[0].value = test_vector[0]
model.rd_addr.value = test_vector[0]
model.wr_en.value = test_vector[2]
model.wr_addr.value = test_vector[3]
model.wr_data.value = test_vector[4]

def tv_out( model, test_vector ):
if test_vector[1] != '?':
assert model.rd_data[0].value == test_vector[1]
assert model.rd_data.value == test_vector[1]

# Run the test

Expand Down Expand Up @@ -88,14 +88,14 @@ def test_regfile_1R1Wconst0( dump_vcd, test_verilog ):
# Define functions mapping the test vector to ports in model

def tv_in( model, test_vector ):
model.rd_addr[0].value = test_vector[0]
model.rd_addr.value = test_vector[0]
model.wr_en.value = test_vector[2]
model.wr_addr.value = test_vector[3]
model.wr_data.value = test_vector[4]

def tv_out( model, test_vector ):
if test_vector[1] != '?':
assert model.rd_data[0].value == test_vector[1]
assert model.rd_data.value == test_vector[1]

# Run the test

Expand Down