This repository is a collection of BSV modules and Verilog code for common building blocks.
There are two macros used by this package for special configurations
EHR_USE_VERILOG
- With this defined,Ehr.bsv
usesVerilogEHR.bsv
to makemkEhr
andmkEhrU
use Verilog EHRs.SRAMUTIL_SRAM
- With this defined,SRAMUtil.bsv
uses SRAMs fromSRAMCore.bsv
instead of BRAM.
List of packages and links to their automatically generated documentation:
- ClientServerUtil
- ClockGate
- CompareProvisos
- ConcatReg
- Ehr
- FIFOG
- GenericAtomicMem
- MemUtil
- OneWriteReg
- PerfMonitor (and PerfMonitorConnectal)
- PolymorphicMem
- Port
- PortUtil
- PrintTrace
- RWBram
- RegFileUtil
- RegUtil
- SRAMUtil
- SafeCounter
- ScheduleMonitor
- SearchFIFO
- ServerUtil
- ShiftRegister
- StmtFSMUtil
- StringUtils