Machine: restrict more CSR registers fields to read only and correct …

…CYCLE CSR updates Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
cvut · Dec 2, 2023 · daf63f9 · daf63f9
1 parent 13d07e0
commit daf63f9
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Showing 4 changed files with 25 additions and 9 deletions.
diff --git a/src/machine/core.cpp b/src/machine/core.cpp
@@ -200,7 +200,6 @@ FetchState Core::fetch(PCInterstage pc, bool skip_break) {
 
     if (control_state != nullptr) {
         control_state->increment_internal(CSR::Id::MCYCLE, 1);
-        control_state->write_internal(CSR::Id::CYCLE, control_state->read_internal(CSR::Id::MCYCLE));
     }
 
     if (control_state != nullptr && excause == EXCAUSE_NONE) {

diff --git a/src/machine/csr/controlstate.cpp b/src/machine/csr/controlstate.cpp
@@ -86,6 +86,16 @@ namespace machine { namespace CSR {
         default_wlrl_write_handler(desc, reg, val);
     }
 
+    void ControlState::mcycle_wlrl_write_handler(
+        const RegisterDesc &desc,
+        RegisterValue &reg,
+        RegisterValue val) {
+        Q_UNUSED(desc)
+        reg = val;
+        register_data[Id::CYCLE] = val;
+        write_signal(Id::CYCLE, register_data[Id::CYCLE]);
+    }
+
     bool ControlState::operator==(const ControlState &other) const {
         return register_data == other.register_data;
     }

diff --git a/src/machine/csr/controlstate.h b/src/machine/csr/controlstate.h
@@ -158,6 +158,10 @@ namespace machine { namespace CSR {
             const RegisterDesc &desc,
             RegisterValue &reg,
             RegisterValue val);
+        void mcycle_wlrl_write_handler(
+            const RegisterDesc &desc,
+            RegisterValue &reg,
+            RegisterValue val);
     };
 
     struct RegisterDesc {
@@ -202,19 +206,22 @@ namespace machine { namespace CSR {
                         0, 0x807FFFEA, &ControlState::mstatus_wlrl_write_handler,
                         {Field::mstatus::fields, Field::mstatus::count} },
         [Id::MISA] = { "misa", 0x301_csr, "Machine ISA Register.",
-                       (1 << 30) | (1 << ('I'-'A')) | (1 << ('M'-'A')), 0},
-        [Id::MIE] = { "mie", 0x304_csr, "Machine interrupt-enable register." },
-        [Id::MTVEC] = { "mtvec", 0x305_csr, "Machine trap-handler base address." },
+                        (1 << 30) | (1 << ('I'-'A')) | (1 << ('M'-'A')), 0},
+        [Id::MIE] = { "mie", 0x304_csr, "Machine interrupt-enable register.",
+                        0, 0x00ff0AAA},
+        [Id::MTVEC] = { "mtvec", 0x305_csr, "Machine trap-handler base address."},
         [Id::MSCRATCH] = { "mscratch", 0x340_csr, "Scratch register for machine trap handlers." },
         [Id::MEPC] = { "mepc", 0x341_csr, "Machine exception program counter." },
         [Id::MCAUSE] = { "mcause", 0x342_csr, "Machine trap cause." },
         [Id::MTVAL] = { "mtval", 0x343_csr, "Machine bad address or instruction." },
-        [Id::MIP] = { "mip", 0x344_csr, "Machine interrupt pending." },
-        [Id::MTINST] = { "mtinsr", 0x34A_csr, "Machine trap instruction (transformed)." },
+        [Id::MIP] = { "mip", 0x344_csr, "Machine interrupt pending.",
+                        0, 0x00000222},
+        [Id::MTINST] = { "mtinst", 0x34A_csr, "Machine trap instruction (transformed)." },
         [Id::MTVAL2] = { "mtval2", 0x34B_csr, "Machine bad guest physical address." },
         // Machine Counter/Timers
-        [Id::MCYCLE] = { "mcycle", 0xB00_csr, "Machine cycle counter." },
-        [Id::MINSTRET] = { "minstret", 0xB02_csr, "Machine instructions-retired counter." },
+        [Id::MCYCLE] = { "mcycle", 0xB00_csr, "Machine cycle counter.",
+                        0, (register_storage_t)0xffffffffffffffff, &ControlState::mcycle_wlrl_write_handler},
+        [Id::MINSTRET] = { "minstret", 0xB02_csr, "Machine instructions-retired counter."},
     } };
 
     /** Lookup from CSR address (value used in instruction) to internal id (index in continuous

diff --git a/tests/cli/stalls/stdout.txt b/tests/cli/stalls/stdout.txt
@@ -2,4 +2,4 @@ Machine stopped on BREAK exception.
 Machine state report:
 PC:0x00000244
 R0:0x00000000 R1:0x00000011 R2:0x00000022 R3:0x00000033 R4:0x00000000 R5:0x00000055 R6:0x00000000 R7:0x00000000 R8:0x00000000 R9:0x00000000 R10:0x00000000 R11:0x00000000 R12:0x00000000 R13:0x00000000 R14:0x00000000 R15:0x00000000 R16:0x00000000 R17:0x00000000 R18:0x00000000 R19:0x00000000 R20:0x00000000 R21:0x00000011 R22:0x00000022 R23:0x00000033 R24:0x00000044 R25:0x00000055 R26:0x00000000 R27:0x00000000 R28:0x00000000 R29:0x00000000 R30:0x00000000 R31:0x00000000
-cycle: 0x00000000 mvendorid: 0x00000000 marchid: 0x00000000 mimpid: 0x00000000 mhardid: 0x00000000 mstatus: 0x00000000 misa: 0x40001100 mie: 0x00000000 mtvec: 0x00000000 mscratch: 0x00000000 mepc: 0x00000240 mcause: 0x00000003 mtval: 0x00000000 mip: 0x00000000 mtinsr: 0x00000000 mtval2: 0x00000000 mcycle: 0x0000000c minstret: 0x0000000b
+cycle: 0x0000000c mvendorid: 0x00000000 marchid: 0x00000000 mimpid: 0x00000000 mhardid: 0x00000000 mstatus: 0x00000000 misa: 0x40001100 mie: 0x00000000 mtvec: 0x00000000 mscratch: 0x00000000 mepc: 0x00000240 mcause: 0x00000003 mtval: 0x00000000 mip: 0x00000000 mtinst: 0x00000000 mtval2: 0x00000000 mcycle: 0x0000000c minstret: 0x0000000b