GUI: RISC-V ACLINT MSWI mapping added into resources/samples/template.S

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
cvut · Nov 29, 2023 · f5f8802 · f5f8802
1 parent 8c8dc07
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Showing 2 changed files with 20 additions and 5 deletions.
diff --git a/README.md b/README.md
@@ -245,7 +245,7 @@ even that is not an option then default directory when the emulator has been sta
 ### Peripherals
 
 <details>
-  <summary>Emuated LCD, knobs, buttons, serial port...</summary>
+  <summary>Emuated LCD, knobs, buttons, serial port, timer...</summary>
 
 The simulator implements emulation of two peripherals for now.
 
@@ -310,7 +310,19 @@ Limitation: actual concept of memory view updates and access does not allow to r
 I/O memory content. It is possible to write into framebuffer memory when cached (from CPU perspective) access to memory
 is selected.
 
-</details>  
+The basic implementation of RISC-V Advanced Core Local Interruptor
+is implemented with basic support for
+
+- Machine-level Timer Device (MTIMER)
+- Machine-level Software Interrupt Device (MSWI)
+
+```
+#define ACLINT_MSWI        0xfffd0000 // core 0 SW interrupt request
+#define ACLINT_MTIMECMP    0xfffd4000 // core 0 compare value
+#define ACLINT_MTIME       0xfffdbff8 // timer base 10 MHz
+```
+
+</details>
 
 ### Interrupts and Control and Status Registers
 
@@ -323,9 +335,10 @@ List of interrupt sources:
 
 | Irq number | Cause/Status Bit | Source                                       |
 |-----------:|-----------------:|:---------------------------------------------|
+| 3          | 3                | Machine software interrupt request           |
 | 7          | 7                | Machine timer interrupt                      |
-| 16 / HW0   | 16               | There is received character ready to be read |
-| 17 / HW1   | 17               | Serial port ready to accept character to Tx  |
+| 16         | 16               | There is received character ready to be read |
+| 17         | 17               | Serial port ready to accept character to Tx  |
 
 Following Control Status registers are recognized
 

diff --git a/src/gui/resources/samples/template.S b/src/gui/resources/samples/template.S
@@ -65,12 +65,14 @@
 .equ LCD_FB_START,          0xffe00000
 .equ LCD_FB_END,            0xffe4afff
 
-// RISC-V ACLINT MTIMER memory mapped peripheral
+// RISC-V ACLINT MSWI and MTIMER memory mapped peripherals
+.equ ACLINT_MSWI,           0xfffd0000 // core 0 SW interrupt request
 .equ ACLINT_MTIMECMP,       0xfffd4000 // core 0 compare value
 .equ ACLINT_MTIME,          0xfffdbff8 // timer base 10 MHz
 
 // Mapping of interrupts
 // Irq number   mcause Bit   Source
+//   3           3         ACLINT MSWI
 //   7           7         MTIME reached value of MTIMECMP
 //  16          16         There is received character ready to be read
 //  17          17         Serial port ready to accept character to Tx