Code

Csr support#49

Code

Merged

ppisa merged 28 commits intomastercvut/qtrvsim:masterfrom csr-supportcvut/qtrvsim:csr-supportCopy head branch name to clipboardOct 24, 2022

+714-575

Commits

Commits on Sep 30, 2022

• Project: fix logging category structure for instruction.cpp

  jdupak

  committed
  c35a488

• Machine: add argument description for CSR imm

  jdupak

  committed
  4f3fb93

• Machine: fix typo

  jdupak

  committed
  57d749f

• Machine: log mismatched instruction codes as error

  jdupak

  committed
  5e0dbe1

• Machine: split system instruction table and add CSR instructions as nops

  jdupak

  committed
  a852c22

• Project: clang-format

  Show description for 8a1eef2
  jdupak

  committed
  8a1eef2

• Common: fix inconsistent includes in bit_ops

  jdupak

  committed
  8bf5185

• Machine: add illegal instruction (cpp) exception

  jdupak

  committed
  9a90bd5

• Machine&GUI: adjust machine CSR structs to RISV-V, adjust gui dock, add some basic registers

  jdupak

  committed
  c8f1590

• Machine: auto type for instruction flags

  Show description for cf48d67
  jdupak

  committed
  cf48d67

Commits on Oct 19, 2022

• Machine: CSR: implement CSR instructions

  jdupak

  committed
  a5a5458

• Machine: CSR: resolve printf format warnings

  jdupak

  committed
  bed7d23

• Machine: CSR: update cli test expected output

  Show description for a931860
  jdupak

  committed
  a931860

• Machine: CSR: recognize csr register name in assembler

  jdupak

  committed
  d90fb8f

• Machine: CSR: correct order of args

  jdupak

  committed
  15a79fd

• Machine: CSR: fix ambiguous conversion to RegisterValue

  jdupak

  committed
  19fcdfb

• Machine: CSR: fix permission bit checks

  jdupak

  committed
  95277a0

• Machine: CSR: only insert one stall before csr instruction

  jdupak

  committed
  43974d1

Commits on Oct 21, 2022

• Machine: CSR: move address map from controlstate to header file

  jdupak

  committed
  fd589ed

Commits on Oct 22, 2022

• Machine: CSR: move register name handling from assembler to instruction.cpp and add dissemble support

  jdupak

  committed
  57b298c

• GUI: CSR: syntax highlight CSR reg names

  jdupak

  committed
  f0f6f28

• GUI: syntax highlight remove dead code

  jdupak

  committed
  483841d

• GUI: syntax highlight fix formatting

  jdupak

  committed
  8dd1f4d

• GUI: syntax highlight remove deprecated qt fallback

  Show description for 5bceb99
  jdupak

  committed
  5bceb99

• GUI: syntax highlight refactor

  jdupak

  committed
  fbbae06

Commits on Oct 23, 2022

• Machine: CSR: disassemble CSR register based on the mnemonic register settings

  jdupak

  committed
  0a30512

• Machine: CSR: refactor to hex values

  jdupak

  committed
  33051ae

• GUI: save mnemonic registers settings

  jdupak

  committed
  4d5aa16