CDIM-SoC

SoC for CQU Dual Issue Machine

Board

128M DDR3 MIG
256K BRAM for U-Boot
AXI Ethernet Lite
CONFREG (Used for Real-time Clock)
AXI Interrupt Controller (Convert rising edge IRQ from AXI Ethernet lite to active high level IRQ for CPU)

AXI Ethernet Link Down in Linux

If you program this soc and didn't press the reset from cold, the AXI Ethernet Lite in Linux will show the link down. Although the ethernet seems fine in U-Boot.

The solution is to press the reset button on the board to reset the ethernet phy and the whole system.
AXI Ethernet Lite transmit timeout in Linux

If the Enable Asynchronous Clock operation is enabled in AXI Interrupt Controller, the CPU will not receive any ethernet interrupt from AXI Interrupt Controller (Who can tell me why?).

This problem can be checked by cat /proc/interrupts and check whether the eth0 interrupt count is zero.

If this option is enabled automatically by Vivado Block Design, you should manually disable this option.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
CDIM-SoC.hw		CDIM-SoC.hw
CDIM-SoC.ip_user_files		CDIM-SoC.ip_user_files
CDIM-SoC.srcs		CDIM-SoC.srcs
CDIM-SoC.xpr		CDIM-SoC.xpr
README.md		README.md
nscscc-ddr.ucf		nscscc-ddr.ucf