Merge pull request #10 from frank-w/4.16-main

4.16 main

.gitignore

@@ -131,3 +131,8 @@ all.config
 #Automatically generated by ASN.1 compiler
 net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c
 net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h
+
+#own
+arch/arm/boot/zImage-dtb
+uImage
+uboot/

Documentation/devicetree/bindings/display/panel/panel-common.txt

@@ -38,7 +38,7 @@ Display Timings
  require specific display timings. The panel-timing subnode expresses those
  timings as specified in the timing subnode section of the display timing
  bindings defined in
- Documentation/devicetree/bindings/display/display-timing.txt.
+ Documentation/devicetree/bindings/display/panel/display-timing.txt.
 
 
 Connectivity

Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

@@ -25,6 +25,7 @@ Required Properties:
  - "renesas,dmac-r8a7794" (R-Car E2)
  - "renesas,dmac-r8a7795" (R-Car H3)
  - "renesas,dmac-r8a7796" (R-Car M3-W)
+ - "renesas,dmac-r8a77965" (R-Car M3-N)
  - "renesas,dmac-r8a77970" (R-Car V3M)
 
 - reg: base address and length of the registers block for the DMAC

Documentation/devicetree/bindings/net/renesas,ravb.txt

@@ -17,6 +17,7 @@ Required properties:
 
  - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
  - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+ - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
  - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
  - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
  - "renesas,etheravb-r8a77995" for the R8A77995 SoC.

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

@@ -55,9 +55,9 @@ pins it needs, and how they should be configured, with regard to muxer
 configuration, drive strength and pullups. If one of these options is
 not set, its actual value will be unspecified.
 
-This driver supports the generic pin multiplexing and configuration
-bindings. For details on each properties, you can refer to
-./pinctrl-bindings.txt.
+Allwinner A1X Pin Controller supports the generic pin multiplexing and
+configuration bindings. For details on each properties, you can refer to
+ ./pinctrl-bindings.txt.
 
 Required sub-node properties:
  - pins

Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt

@@ -21,7 +21,7 @@ Required properties:
 - interrupts : identifier to the device interrupt
 - clocks : a list of phandle + clock-specifier pairs, one for each
  entry in clock names.
-- clocks-names :
+- clock-names :
  * "xtal" for external xtal clock identifier
  * "pclk" for the bus core clock, either the clk81 clock or the gate clock
  * "baud" for the source of the baudrate generator, can be either the xtal

Documentation/devicetree/bindings/serial/mvebu-uart.txt

@@ -24,7 +24,7 @@ Required properties:
  - Must contain two elements for the extended variant of the IP
  (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
  respectively the UART TX interrupt and the UART RX interrupt. A
- corresponding interrupts-names property must be defined.
+ corresponding interrupt-names property must be defined.
  - For backward compatibility reasons, a single element interrupts
  property is also supported for the standard variant of the IP,
  containing only the UART sum interrupt. This form is deprecated

Documentation/devicetree/bindings/serial/renesas,sci-serial.txt

@@ -41,6 +41,8 @@ Required properties:
  - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
  - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
  - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
+ - "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART.
+ - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART.
  - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
  - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
  - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.

Documentation/devicetree/bindings/vendor-prefixes.txt

@@ -181,6 +181,7 @@ karo Ka-Ro electronics GmbH
 keithkoep Keith & Koep GmbH
 keymile Keymile GmbH
 khadas Khadas
+kiebackpeter Kieback & Peter GmbH
 kinetic Kinetic Technologies
 kingnovel Kingnovel Technology Co., Ltd.
 kosagi Sutajio Ko-Usagi PTE Ltd.

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 4
 PATCHLEVEL = 16
-SUBLEVEL = 15
+SUBLEVEL = 18
 EXTRAVERSION =
 NAME = Fearless Coyote
 

arch/arm/boot/compressed/Makefile

@@ -117,11 +117,9 @@ ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
 asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
-KBSS_SZ = $(shell $(CROSS_COMPILE)nm $(obj)/../../../../vmlinux | \
- perl -e 'while (<>) { \
- $$bss_start=hex($$1) if /^([[:xdigit:]]+) B __bss_start$$/; \
- $$bss_end=hex($$1) if /^([[:xdigit:]]+) B __bss_stop$$/; \
- }; printf "%d\n", $$bss_end - $$bss_start;')
+KBSS_SZ = $(shell echo $$(($$($(CROSS_COMPILE)nm $(obj)/../../../../vmlinux | \
+ sed -n -e 's/^\([^ ]*\) [AB] __bss_start$$/-0x\1/p' \
+ -e 's/^\([^ ]*\) [AB] __bss_stop$$/+0x\1/p') )) )
 LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
 # Supply ZRELADDR to the decompressor via a linker symbol.
 ifneq ($(CONFIG_AUTO_ZRELADDR),y)

arch/arm/boot/compressed/head.S

@@ -29,19 +29,19 @@
 #if defined(CONFIG_DEBUG_ICEDCC)
 
 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
- .macro loadsp, rb, tmp
+ .macro loadsp, rb, tmp1, tmp2
  .endm
  .macro writeb, ch, rb
  mcr p14, 0, \ch, c0, c5, 0
  .endm
 #elif defined(CONFIG_CPU_XSCALE)
- .macro loadsp, rb, tmp
+ .macro loadsp, rb, tmp1, tmp2
  .endm
  .macro writeb, ch, rb
  mcr p14, 0, \ch, c8, c0, 0
  .endm
 #else
- .macro loadsp, rb, tmp
+ .macro loadsp, rb, tmp1, tmp2
  .endm
  .macro writeb, ch, rb
  mcr p14, 0, \ch, c1, c0, 0
@@ -57,7 +57,7 @@
  .endm
 
 #if defined(CONFIG_ARCH_SA1100)
- .macro loadsp, rb, tmp
+ .macro loadsp, rb, tmp1, tmp2
  mov \rb, #0x80000000 @ physical base address
 #ifdef CONFIG_DEBUG_LL_SER3
  add \rb, \rb, #0x00050000 @ Ser3
@@ -66,8 +66,8 @@
 #endif
  .endm
 #else
- .macro loadsp, rb, tmp
- addruart \rb, \tmp
+ .macro loadsp, rb, tmp1, tmp2
+ addruart \rb, \tmp1, \tmp2
  .endm
 #endif
 #endif
@@ -561,8 +561,6 @@ not_relocated: mov r0, #0
  bl decompress_kernel
  bl cache_clean_flush
  bl cache_off
- mov r1, r7 @ restore architecture number
- mov r2, r8 @ restore atags pointer
 
 #ifdef CONFIG_ARM_VIRT_EXT
  mrs r0, spsr @ Get saved CPU boot mode
@@ -1297,7 +1295,7 @@ phex: adr r3, phexbuf
  b 1b
 
 @ puts corrupts {r0, r1, r2, r3}
-puts: loadsp r3, r1
+puts: loadsp r3, r2, r1
 1: ldrb r2, [r0], #1
  teq r2, #0
  moveq pc, lr
@@ -1314,8 +1312,8 @@ puts: loadsp r3, r1
 @ putc corrupts {r0, r1, r2, r3}
 putc:
  mov r2, r0
+ loadsp r3, r1, r0
  mov r0, #0
- loadsp r3, r1
  b 2b
 
 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
@@ -1365,6 +1363,8 @@ __hyp_reentry_vectors:
 
 __enter_kernel:
  mov r0, #0 @ must be 0
+ mov r1, r7 @ restore architecture number
+ mov r2, r8 @ restore atags pointer
  ARM( mov pc, r4 ) @ call kernel
  M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
  THUMB( bx r4 ) @ entry point is always ARM for A/R classes

arch/arm/boot/dts/bcm-cygnus.dtsi

@@ -69,7 +69,7 @@
  timer@20200 {
  compatible = "arm,cortex-a9-global-timer";
  reg = <0x20200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  clocks = <&periph_clk>;
  };
 

arch/arm/boot/dts/da850.dtsi

@@ -46,8 +46,6 @@
  pmx_core: pinmux@14120 {
  compatible = "pinctrl-single";
  reg = <0x14120 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
  #pinctrl-cells = <2>;
  pinctrl-single,bit-per-mux;
  pinctrl-single,register-width = <32>;

arch/arm/boot/dts/dm8148-evm.dts

@@ -10,7 +10,7 @@
 
 / {
  model = "DM8148 EVM";
- compatible = "ti,dm8148-evm", "ti,dm8148";
+ compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
 
  memory@80000000 {
  device_type = "memory";

arch/arm/boot/dts/dm8148-t410.dts

@@ -9,7 +9,7 @@
 
 / {
  model = "HP t410 Smart Zero Client";
- compatible = "hp,t410", "ti,dm8148";
+ compatible = "hp,t410", "ti,dm8148", "ti,dm814";
 
  memory@80000000 {
  device_type = "memory";

arch/arm/boot/dts/dm8168-evm.dts

@@ -10,7 +10,7 @@
 
 / {
  model = "DM8168 EVM";
- compatible = "ti,dm8168-evm", "ti,dm8168";
+ compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";
 
  memory@80000000 {
  device_type = "memory";

arch/arm/boot/dts/dra62x-j5eco-evm.dts

@@ -10,7 +10,7 @@
 
 / {
  model = "DRA62x J5 Eco EVM";
- compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148";
+ compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
 
  memory@80000000 {
  device_type = "memory";

arch/arm/boot/dts/imx51-zii-rdu1.dts

@@ -518,7 +518,7 @@
  };
 
  touchscreen@20 {
- compatible = "syna,rmi4_i2c";
+ compatible = "syna,rmi4-i2c";
  reg = <0x20>;
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_ts>;
@@ -536,8 +536,8 @@
 
  rmi4-f11@11 {
  reg = <0x11>;
- touch-inverted-y;
- touch-swapped-x-y;
+ touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
  syna,sensor-type = <1>;
  };
  };

arch/arm/boot/dts/logicpd-som-lv.dtsi

@@ -26,7 +26,7 @@
  gpio = <&gpio1 3 0>; /* gpio_3 */
  startup-delay-us = <70000>;
  enable-active-high;
- vin-supply = <&vmmc2>;
+ vin-supply = <&vaux3>;
  };
 
  /* HS USB Host PHY on PORT 1 */
@@ -82,6 +82,7 @@
  twl_audio: audio {
  compatible = "ti,twl4030-audio";
  codec {
+ ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  };
  };
  };
@@ -195,6 +196,7 @@
  pinctrl-single,pins = <
  OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
  >;
  };
 };
@@ -209,7 +211,7 @@
  };
  wl127x_gpio: pinmux_wl127x_gpio_pin {
  pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
+ OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
  OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
  >;
  };
@@ -244,6 +246,11 @@
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
 
+&vaux3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
 &twl {
  twl_power: power {
  compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";

arch/arm/boot/dts/omap4.dtsi

@@ -163,10 +163,10 @@
 
  cm2: cm2@8000 {
  compatible = "ti,omap4-cm2", "simple-bus";
- reg = <0x8000 0x3000>;
+ reg = <0x8000 0x2000>;
  #address-cells = <1>;
  #size-cells = <1>;
- ranges = <0 0x8000 0x3000>;
+ ranges = <0 0x8000 0x2000>;
 
  cm2_clocks: clocks {
  #address-cells = <1>;
@@ -250,11 +250,11 @@
 
  prm: prm@6000 {
  compatible = "ti,omap4-prm";
- reg = <0x6000 0x3000>;
+ reg = <0x6000 0x2000>;
  interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  #address-cells = <1>;
  #size-cells = <1>;
- ranges = <0 0x6000 0x3000>;
+ ranges = <0 0x6000 0x2000>;
 
  prm_clocks: clocks {
  #address-cells = <1>;

arch/arm/kernel/machine_kexec.c

@@ -95,6 +95,27 @@ void machine_crash_nonpanic_core(void *unused)
  cpu_relax();
 }
 
+void crash_smp_send_stop(void)
+{
+ static int cpus_stopped;
+ unsigned long msecs;
+
+ if (cpus_stopped)
+ return;
+
+ atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
+ smp_call_function(machine_crash_nonpanic_core, NULL, false);
+ msecs = 1000; /* Wait at most a second for the other cpus to stop */
+ while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
+ mdelay(1);
+ msecs--;
+ }
+ if (atomic_read(&waiting_for_crash_ipi) > 0)
+ pr_warn("Non-crashing CPUs did not react to IPI\n");
+
+ cpus_stopped = 1;
+}
+
 static void machine_kexec_mask_interrupts(void)
 {
  unsigned int i;
@@ -120,19 +141,8 @@ static void machine_kexec_mask_interrupts(void)
 
 void machine_crash_shutdown(struct pt_regs *regs)
 {
- unsigned long msecs;
-
  local_irq_disable();
-
- atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
- smp_call_function(machine_crash_nonpanic_core, NULL, false);
- msecs = 1000; /* Wait at most a second for the other cpus to stop */
- while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
- mdelay(1);
- msecs--;
- }
- if (atomic_read(&waiting_for_crash_ipi) > 0)
- pr_warn("Non-crashing CPUs did not react to IPI\n");
+ crash_smp_send_stop();
 
  crash_save_cpu(regs, smp_processor_id());
  machine_kexec_mask_interrupts();