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Sync up with Linus #101
Sync up with Linus #101
Commits on Aug 22, 2015
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f2fs: kill dead code in __insert_extent_tree
After commit 0f825ee ("f2fs: add new interfaces for extent tree"), f2fs_init_extent_tree becomes the only caller of __insert_extent_tree, and in f2fs_init_extent_tree, we will only insert extent node in an empty tree, so __try_{back,front}_merge in __insert_extent_tree will never be called. This patch removes these dead codes, besides, rename __insert_extent_tree to __init_extent_tree for readability. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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f2fs: split __insert_extent_tree_ret for readability
This patch splits __insert_extent_tree_ret into __try_merge_extent_node & __insert_extent_tree for code readability. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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f2fs: lookup neighbor extent nodes for merging later
In __lookup_extent_tree_ret we will not try to find neighbor nodes if we find the target node, in this condition, we will lost the chance to merge the new mapping with exist extent node later. So our extent cache of inode will be fragmented after overwrite exist file, we can see the number of extent node increases intensively in following test case: dd if=/dev/zero of=/mnt/f2fs/4m bs=4K count=1024 Extent Cache: - Hit Count: L1-1:0 L1-2:0 L2:0 - Hit Ratio: 0% (0 / 3072) - Inner Struct Count: tree: 1, node: 1 dd if=/dev/zero of=/mnt/f2fs/4m bs=4K count=1024 conv=notrunc Extent Cache: - Hit Count: L1-1:2048 L1-2:0 L2:0 - Hit Ratio: 33% (2048 / 6144) - Inner Struct Count: tree: 1, node: 961 This patch fixes to lookup neighbors of target node for further merging. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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powerpc/powernv: Fix mis-merge of OPAL support for LEDS driver
When I merged the OPAL support for the powernv LEDS driver I missed a hunk. This is slightly modified from the original patch, as the original added code to opal-api.h which is not in the skiboot version, which is discouraged. Instead those values are moved into the driver, which is the only place they are used. Fixes: 8a8d918 ("powerpc/powernv: Add OPAL interfaces for accessing and modifying system LED states") Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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cxl: Remove use of macro DEFINE_PCI_DEVICE_TABLE
Macro DEFINE_PCI_DEVICE_TABLE is deprecated. So, here use struct pci_device_id instead of DEFINE_PCI_DEVICE_TABLE with the goal of getting rid of this macro completely. The Coccinelle semantic patch that performs this transformation is as follows: @@ identifier a; declarer name DEFINE_PCI_DEVICE_TABLE; initializer i; @@ - DEFINE_PCI_DEVICE_TABLE(a) + const struct pci_device_id a[] = i; Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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Commits on Aug 24, 2015
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pinctrl: sh-pfc: Implement pinconf power-source param for voltage swi…
…tching The pfc in the R8A7790 (and probably others in the R-Car gen 2 family) supports switching SDHI signals between 3.3V and 1.8V nominal voltage, and the SD driver should do that when switching to and from UHS modes. Add a flag for pins that have configurable I/O voltage and SoC operations to get and set the nominal voltage. Implement the pinconf power-source parameter using these operations. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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arm64: Fix source code file path in comments
Architecture specific code for i386 and x86_64 was unified and merged to the arch/x86. This patch fix old path of x86 architecture in a comment from the arch/arm64/include/asm/fixmap.h. Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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of/fdt: make memblock maximum physical address arch configurable
When parsing the memory nodes to populate the memblock memory table, we check against high and low limits and clip any memory that exceeds either one of them. However, for arm64, the high limit of (phys_addr_t)~0 is not very meaningful, since phys_addr_t is 64 bits (i.e., no limit) but there may be other constraints that limit the memory ranges that we can support. So rename MAX_PHYS_ADDR to MAX_MEMBLOCK_ADDR (for clarity) and only define it if the arch does not supply a definition of its own. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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arm64: set MAX_MEMBLOCK_ADDR according to linear region size
The linear region size of a 39-bit VA kernel is only 256 GB, which may be insufficient to cover all of system RAM, even on platforms that have much less than 256 GB of memory but which is laid out very sparsely. So make sure we clip the memory we will not be able to map before installing it into the memblock memory table, by setting MAX_MEMBLOCK_ADDR accordingly. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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arm64: makefile: fix perf_callchain.o kconfig dependency
Commit 4b3dc96 ("arm64: force CONFIG_SMP=y and remove redundant #ifdefs") incorrectly resolved a conflict on arch/arm64/kernel/Makefile which resulted in a partial revert of 52da443 ("arm64: perf: factor out callchain code"), leading to perf_callchain.o depending on CONFIG_HW_PERF_EVENTS instead of CONFIG_PERF_EVENTS. This patch restores the kconfig dependency for perf_callchain.o. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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f2fs: use __GFP_NOFAIL to avoid infinite loop
__GFP_NOFAIL can avoid retrying the whole path of kmem_cache_alloc and bio_alloc. And, it also fixes the use cases of GFP_ATOMIC correctly. Suggested-by: Chao Yu <chao2.yu@samsung.com> Reviewed-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Jaegeuk Kim committedAug 24, 2015 Configuration menu - View commit details
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f2fs: fix wrong pointer access during try_to_free_nids
If we release the lock in list_for_each_entry_safe, we can lose the tmp pointer by alloc_nid. Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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f2fs: atomically set inode->i_flags
According to commit 5f16f32 ("ext4: atomically set inode->i_flags in ext4_set_inode_flags()"). Signed-off-by: Zhang Zhen <zhenzhang.zhang@huawei.com> Reviewed-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Zhang Zhen authored and Jaegeuk Kim committedAug 24, 2015 Configuration menu - View commit details
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f2fs: avoid unneeded initializing when converting inline dentry
When converting inline dentry, we will zero out target dentry page before duplicating data of inline dentry into target page, it become overhead since inline dentry size is not small. So this patch tries to remove unneeded initializing in the space of target dentry page. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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f2fs: handle f2fs_truncate error correctly
This patch fixes to return error number of f2fs_truncate, so that we can handle the error correctly in callers. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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f2fs: fix to release inode correctly
In following call stack, if unfortunately we lose all chances to truncate inode page in remove_inode_page, eventually we will add the nid allocated previously into free nid cache, this nid is with NID_NEW status and with NEW_ADDR in its blkaddr pointer: - f2fs_create - f2fs_add_link - __f2fs_add_link - init_inode_metadata - new_inode_page - new_node_page - set_node_addr(, NEW_ADDR) - f2fs_init_acl failed - remove_inode_page failed - handle_failed_inode - remove_inode_page failed - iput - f2fs_evict_inode - remove_inode_page failed - alloc_nid_failed cache a nid with valid blkaddr: NEW_ADDR This may not only cause resource leak of previous inode, but also may cause incorrect use of the previous blkaddr which is located in NO.nid node entry when this nid is reused by others. This patch tries to add this inode to orphan list if we fail to truncate inode, so that we can obtain a second chance to release it in orphan recovery flow. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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Commits on Aug 25, 2015
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ARM: uaccess: simplify user access assembly
The user assembly for byte and word accesses was virtually identical. Rather than duplicating this, use a macro instead. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: entry: get rid of asm_trace_hardirqs_on_cond
There's no need for this macro, it can use a default for the condition argument. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: entry: efficiency cleanups
Make the "fast" syscall return path fast again. The addition of IRQ tracing and context tracking has made this path grossly inefficient. We can do much better if these options are enabled if we save the syscall return code on the stack - we then don't need to save a bunch of registers around every single callout to C code. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: entry: ensure that IRQs are enabled when calling syscall_trace_e…
…xit() The audit code looks like it's been written to cope with being called with IRQs enabled. However, it's unclear whether IRQs should be enabled or disabled when calling the syscall tracing infrastructure. Right now, sometimes we call this with IRQs enabled, and other times with IRQs disabled. Opt for IRQs being enabled for consistency. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll get errors like this if you try to pinmux them via the devicetree: zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand" Probably a typo while creating these tables. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: extraxfs: fix returnvar.cocci warnings
Remove unneeded variable used to store return value. Generated by: scripts/coccinelle/misc/returnvar.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: imx6ul: Remove .owner field
platform_driver does not need to set an owner as it will be populated by the driver core. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ARM: mm: improve do_ldrd_abort macro
Improve the do_ldrd_abort macro code - firstly, it inefficiently checks for the LDRD encoding by doing a multi-stage test of various bits. This can be simplified by generating a mask, bitmasking the instruction and then comparing the result. Secondly, we want to be able to test the result rather than branching to do_DataAbort, so remove the branch at the end and rename the macro to 'teq_ldrd' to reflect it's new usage. teq_ldrd macro returns 'eq' if the instruction was a LDRD. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: uaccess: provide uaccess_save_and_enable() and uaccess_restore()
Provide uaccess_save_and_enable() and uaccess_restore() to permit control of userspace visibility to the kernel, and hook these into the appropriate places in the kernel where we need to access userspace. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: 8421/1: smp: Collapse arch_cpu_idle_dead() into cpu_die()
The only caller of cpu_die() on ARM is arch_cpu_idle_dead(), so let's simplify the code by renaming cpu_die() to arch_cpu_idle_dead(). While were here, drop the __ref annotation because __cpuinit is gone nowadays. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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dlm: fix lvb copy for user locks
For a userland lock request, the previous and current lock modes are used to decide when the lvb should be copied back to the user. The wrong previous value was used, so that it always matched the current value. This caused the lvb to be copied back to the user in the wrong cases. Signed-off-by: David Teigland <teigland@redhat.com>
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Commits on Aug 26, 2015
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pinctrl: baytrail: Use raw_spinlock for locking
The Intel Baytrail pinctrl driver implements irqchip callbacks which are called with desc->lock raw_spinlock held. In mainline this is fine because spinlock resolves to raw_spinlock. However, running the same code in -rt we get: BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0 Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13 ... Call Trace: <IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61 [<ffffffff81077e17>] ___might_sleep+0xe7/0x170 [<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50 [<ffffffff812e3b88>] byt_gpio_clear_triggering+0x38/0x60 [<ffffffff812e3bc1>] byt_irq_mask+0x11/0x20 [<ffffffff810a7013>] handle_level_irq+0x83/0x150 [<ffffffff810a3457>] generic_handle_irq+0x27/0x40 [<ffffffff812e3a5f>] byt_gpio_irq_handler+0x7f/0xc0 [<ffffffff810050aa>] handle_irq+0xaa/0x190 ... This is because in -rt spinlocks are preemptible so taking the driver private spinlock in irqchip callbacks causes might_sleep() to trigger. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Also shorten the critical section a bit in few places. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: cherryview: Use raw_spinlock for locking
When running -rt kernel and an interrupt happens on a GPIO line controlled by Intel Cherryview/Braswell pinctrl driver we get: BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0 Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16 ... Call Trace: <IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61 [<ffffffff81077e17>] ___might_sleep+0xe7/0x170 [<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50 [<ffffffff812e52ed>] chv_gpio_irq_ack+0x3d/0xa0 [<ffffffff810a72f5>] handle_edge_irq+0x75/0x180 [<ffffffff810a3457>] generic_handle_irq+0x27/0x40 [<ffffffff812e57de>] chv_gpio_irq_handler+0x7e/0x110 [<ffffffff810050aa>] handle_irq+0xaa/0x190 ... This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack() is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock which in -rt is an rt-mutex causing might_sleep() rightfully to complain about sleeping function called from invalid context. In order to keep -rt happy but at the same time make sure that register accesses get serialized, convert the driver to use raw_spinlock instead. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpiolib: add description for gpio irqchip fields in struct gpio_chip
Add missed description for GPIO irqchip fields in struct gpio_chip. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: at91: Use generic irq_{request,release}_resources()
The at91-specific irq_{request,release}_resources() callbacks are identical to the generic ones, modulo the bug fix in 5b76e79 ("gpiolib: irqchip: prevent driver unloading if gpio is used as irq only"). Until commit 8b67a1f ("gpio: don't override irq_*_resources() callbacks"), the buggy at91-specific callbacks were never used, though. Hence drop the at91-specific ones in favor of the generic ones. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: omap: remove wrong irq_domain_remove usage in probe
The bank->chip.irqdomain is uninitialized at the moment when irq_domain_remove() is called, so remove this call. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: omap: switch to use platform_get_irq
Switch OMAP GPIO driver to use platform_get_irq(), because it is not recommened to use platform_get_resource(pdev, IORESOURCE_IRQ, ..) for requesting IRQ resources any more, as they can be not ready yet in case of DT-boot. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: omap: fix omap2_set_gpio_debounce
According to TRMs: Required input line stable = (the value of the GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) × 31, where the value of the GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME bit field is from 0 to 255. But now omap2_set_gpio_debounce() will calculate debounce time and behave incorrectly in the following cases: 1) requested debounce time is !0 and <32 calculated DEBOUNCETIME = 0x1 == 62 us; expected value of DEBOUNCETIME = 0x0 == 31us 2) requested debounce time is 0 calculated DEBOUNCETIME = 0x1 == 62 us; expected: disable debounce and DEBOUNCETIME = 0x0 3) requested debounce time is >32 and <63 calculated DEBOUNCETIME = 0x0 and debounce will be disabled; expected: enable debounce and DEBOUNCETIME = 0x1 == 62 us Hence, rework omap2_set_gpio_debounce() to fix above cases: 1) introduce local variable "enable" and use it to identify when debounce need to be enabled or disabled. Disable debounce if requested debounce time is 0. 2) use below formula for debounce time calculation: debounce = (DIV_ROUND_UP(debounce, 31) - 1) & 0xFF; Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: omap: protect regs access in omap_gpio_irq_handler
The access to HW registers has to be be protected in omap_gpio_irq_handler(), as it may race with code executed on another CPUs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: omap: fix clk_prepare/unprepare usage
As per CCF documentation (clk.txt) the clk_prepare/unprepare APIs are not allowed in atomic context. But now OMAP GPIO driver uses them while applying debounce settings and as part of PM runtime irqsafe operations: - omap_gpio_debounce() is holding the lock with IRQs off. + omap2_set_gpio_debounce() + clk_prepare_enable() + clk_prepare() this one might sleep. - pm_runtime_get_sync() is holding the lock with IRQs off + omap_gpio_runtime_suspend() + raw_spin_lock_irqsave() + omap_gpio_dbck_disable() + clk_disable_unprepare() Hence, fix it by moeving dbclk prepare/unprepare in OMAP GPIO omap_gpio_probe/omap_gpio_remove. Also, while here, ensure that debounce functionality is disabled if clk_get() failed, because otherwise kernel will carsh in omap2_set_gpio_debounce(). Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: max732x: Fix error handling in probe()
This fixes error handling in the function max732x_probe by checking if the calls to the function max732x_readb fail by returning a error code. Signed-off-by: Nicholas Krause <xerofoify@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: sh-pfc: r8a7794: add USB pin groups
Add USB0/1 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: mediatek: Fix multiple registration issue.
Since our common driver need support main chip and PMU at the same time, that means it will register two pinctrl device, and the pinctrl_desc structure should be used two times. But pinctrl_desc use global static definition, then the latest registered pinctrl device will overwrite the old one's, all members in pinctrl_desc will set to the new one's, such as name, pins and pins numbers, etc. This is a bug. Move pinctrl_desc into mtk_pinctrl, assign new value for each pinctrl device to fix it. Cc: stable@vger.kernel.org # v4.1+ Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Reviewed-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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pinctrl: mediatek: Implement wake handler and suspend resume
This patch implement irq_set_wake to get who is wakeup source and setup on suspend resume. Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: vf610: handle level IRQ's properly
The GPIO IRQ controller is able to generate level triggered interrupts, however, these were handled by handle_simple_irq so far which did not take care of IRQ masking. This lead to "nobody cared (try booting with the "irqpoll" option)" stack traces. Use the generic interrupt handlers depending on the IRQ type. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpio: xlp: fix error return code
Return a negative error code on failure. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e1,e2; @@ ( if (\(ret < 0\|ret != 0\)) { ... return ret; } | ret = 0 ) ... when != ret = e1 when != &ret *if(...) { ... when != ret = e2 when forall return ret; } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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MIPS: ath79: irq: IRQCHIP_DECLARE moved to linux/irqchip.h
Remove the ugly cross tree include now that IRQCHIP_DECLARE moved to linux/irqchip.h. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10633/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add MIPS I6400 PRid and cputype identifiers
Add a Processor ID and CPU type for the MIPS I6400 core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Add a CPU_I6400 case to various switch statements, doing the same thing as for CPU_P5600. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add MIPS I6400 probe support
Add a case in cpu_probe_mips for the MIPS I6400 processor ID, which sets the CPU type to the new CPU_I6400. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6
R6 does not support the MIPS MT ASE and the CMP/SMP options so restrict them in order to prevent users from selecting incompatible SMP configuration for R6 cores. We also disable the CPS/SMP option because its support hasn't been added to the CPS code yet. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10637/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: mips-cm: Implement mips_cm_revision
Provide a function to trivially return the version of the CM present in the system, or 0 if no CM is present. The mips_cm_revision() will be used later on to determine the CM register width, so it must not use the regular CM accessors to read the revision register since that will lead to build failures due to recursive inlines. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10655/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CM: Add GCR_L2_CONFIG register accessors
Provide accessor functions for the GCR_L2_CONFIG register introduced with CM3, and define the bits included in the register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CM3: Add support for CM3 L2 cache.
Detect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is present in the system, rather than from Config2 which does not expose the L2 configuration on I6400. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10641/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add platform callback before initializing the L2 cache
Allow platforms to perform platform-specific steps before configuring the L2 cache. This is necessary for platforms with CM3 since the L2 parameters no longer live in the Config2 register. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10642/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: mips-cm: Extend CM accessors for 64-bit CPUs
Previously, the CM accessors were only accessing CM registers as u32 types instead of using the native CM register with. However, newer CMs may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs (CM3) hold all the useful configuration bits in the lower half of the 64-bit registers (at least most of them) so they can still be accessed using the current 32-bit accessors. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.
The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64 so we change its type to unsigned long. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10644/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CPC: Fix type for GCR CPC base reg for 64-bit
The GCR CPC base register is 64-bit on 64-bit processors so use the appropriate field. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10645/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CM: Add support for reporting CM cache errors
The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10646/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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IRQCHIP: irq-mips-gic: Extend GIC accessors for 64-bit CMs
Previously, the GIC accessors were only accessing u32 registers but newer CMs may actually be 64-bit on MIPS64 cores. As a result of which, extended these accessors to support 64-bit reads and writes. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10709/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs
CM3 uses a 64-bit counter and compare registers so add support for them in the GIC counter interrupt. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10648/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB
We are so early in the boot process where we really don't want to stall and wait for CP0 FTLB related changes become visible so just drop the cp0 hazard barrier. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10649/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add default case for the FTLB enable/disable code
Add a default case for the FTLB enable/disable code. This will be used to detect that something went wrong in the set_ftlb_enable() function either because that function knows nothing about the running core, or simply because the core can't turn its FTLB on/off. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cpu-probe: Fix VTLB/FTLB configuration for R6
R6 has dropped the MMUExtDef field from the config4 register and it now returns 0. However, the return value means nothing in that case and the only supported configuration for R6 is the VTLB+FTLB (MMUextDef == 3). As a result, rework the code so that the correct value is set for R6 cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10651/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Set up FTLB probability for I6400
Set up the I6400 FTLB probability similar to P5600 and proAptiv. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: jz4740: Consolidate chained IRQ handler install/remove
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10695/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: pci-ar71xx: Consolidate chained IRQ handler install/remove
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: pci-ar724x: Consolidate chained IRQ handler install/remove
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10697/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: pci-rt3883: Consolidate chained IRQ handler install/remove
Chained irq handlers usually set up handler data as well. We now have a function to set both under irq_desc->lock. Replace the two calls with one. Search and conversion was done with coccinelle. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: irq: Use access helper irq_data_get_affinity_mask()
This is a preparatory patch for moving irq_data struct members. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: alchemy: Use irq_set_chip_handler_name_locked()
Hand in irq_data and avoid the redundant lookup of irq_desc. Originally-from: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: LKML <linux-kernel@vger.kernel.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: bcm63xx: Use irq_set_handler_locked()
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: alchemy: Remove pointless irqdisable/enable
bcsr_csc_handler() is a cascading interrupt handler. It has a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. [ralf@linux-mips.org: Fold in followup fix from Thomas Gleixner.] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10702/ Patchwork: https://patchwork.linux-mips.org/patch/10708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: ath91: Remove pointless irqdisable/enable
The various interrupt flow handlers in ath79 are cascading interrupt handlers. They all have a disable_irq_nosync()/enable_irq() pair around the generic_handle_irq() call. The value of this disable/enable is zero because its a complete noop: disable_irq_nosync() merily increments the disable count without actually masking the interrupt. enable_irq() soleley decrements the disable count without touching the interrupt chip. The interrupt cannot arrive again because the complete call chain runs with interrupts disabled. Remove it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Cc: Jiang Liu <jiang.liu@linux.intel.com> Patchwork: https://patchwork.linux-mips.org/patch/10703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: octeon: Replace the homebrewn flow handler
The gpio interrupt handling of octeon contains a homebrewn flow handler which calls either handle_level_irq or handle_edge_irq depending on the trigger type. Thats an extra conditional and call in the interrupt handling path. The proper way to handle different types and therefor different flows is to update the handler in the irq_set_type() callback. Remove the extra indirection and add the handler update to octeon_irq_ciu_gpio_set_type(). At mapping time it defaults to handle_level_irq which gets updated if the device tree contains a different trigger type. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: David Daney <david.daney@cavium.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: netlogic: Prepare ipi handlers for irq argument removal
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: rt3883: Prepare rt3883_pci_irq_handler for irq argument removal
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: ops-emma2rh: Drop nonsensical db_assert
The db_assert call checks whether the bus_num pointer is non-NULL, but does so after said pointer has been dereferenced by the assignment on the previous line. Thus the check is pointless & likely to have been optimised out by the compiler anyway. The check_args function is static & only ever called from the local file with bus_num being a pointer to an on-stack variable, so the check seems somewhat overzealous anyway. Simply remove it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10692/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.h
The debug.h header provided some MIPS-specific debug macros, which are no longer used at all. Remove them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10693/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it static
There's only one implementation of mips_cpc_phys_base(), and it's only used within the same file, so it doesn't need to be weak, and it doesn't need an extern declaration. Remove the extern mips_cpc_phys_base() declaration and make it static. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove "weak" from platform_maar_init() declaration
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). platform_maar_init() is defined in: - arch/mips/mm/init.c (where it is marked "weak") - arch/mips/mti-malta/malta-memory.c (without annotation) The "weak" attribute on the platform_maar_init() extern declaration applies to the platform-specific definition in arch/mips/mti-malta/malta-memory.c, so both definitions are weak, and which one we get depends on link order. Remove the "weak" attribute from the declaration. That makes the malta definition strong, so it will always be preferred if it is present. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: linux-mips@linux-mips.org Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10682/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: VPE: Exit vpe_release() early if vpe_run() isn't defined
vpe_run() is a weak symbol. If there's no definition of it, its value is zero. If vpe_run is zero, return failure early. We're going to fail anyway, so there's no point in getting a VPE and attempting to load it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: MT: Remove "weak" from vpe_run() declaration
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). That's not a problem for vpe_run() because Kconfig ensures there's never more than one definition: - vpe_run() is defined in arch/mips/kernel/vpe-mt.c if CONFIG_MIPS_VPE_LOADER_MT=y - vpe_run() is defined in arch/mips/mti-malta/malta-amon.c if CONFIG_MIPS_CMP=y - CONFIG_MIPS_VPE_LOADER_MT cannot be set if CONFIG_MIPS_CMP=y But it's simpler to verify correctness if we remove "weak" from the picture and test the config symbols directly. Remove "weak" from the vpe_run() declaration and use #if to test whether a definition should be present. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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f2fs: update extent tree in batches
This patch introduce a new helper f2fs_update_extent_tree_range which can do extent mapping update at a specified range. The main idea is: 1) punch all mapping info in extent node(s) which are at a specified range; 2) try to merge new extent mapping with adjacent node, or failing that, insert the mapping into extent tree as a new node. In order to see the benefit, I add a function for stating time stamping count as below: uint64_t rdtsc(void) { uint32_t lo, hi; __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi)); return (uint64_t)hi << 32 | lo; } My test environment is: ubuntu, intel i7-3770, 16G memory, 256g micron ssd. truncation path: update extent cache from truncate_data_blocks_range non-truncataion path: update extent cache from other paths total: all update paths a) Removing 128MB file which has one extent node mapping whole range of file: 1. dd if=/dev/zero of=/mnt/f2fs/128M bs=1M count=128 2. sync 3. rm /mnt/f2fs/128M Before: total count average truncation: 7651022 32768 233.49 Patched: total count average truncation: 3321 33 100.64 b) fsstress: fsstress -d /mnt/f2fs -l 5 -n 100 -p 20 Test times: 5 times. Before: total count average truncation: 5812480.6 20911.6 277.95 non-truncation: 7783845.6 13440.8 579.12 total: 13596326.2 34352.4 395.79 Patched: total count average truncation: 1281283.0 3041.6 421.25 non-truncation: 7355844.4 13662.8 538.38 total: 8637127.4 16704.4 517.06 1) For the updates in truncation path: - we can see updating in batches leads total tsc and update count reducing explicitly; - besides, for a single batched updating, punching multiple extent nodes in a loop, result in executing more operations, so our average tsc increase intensively. 2) For the updates in non-truncation path: - there is a little improvement, that is because for the scenario that we just need to update in the head or tail of extent node, new interface optimize to update info in extent node directly, rather than removing original extent node for updating and then inserting that updated one into cache as new node. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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ARM: entry: get rid of multiple macro definitions
The following structure is just asking for trouble: #ifdef CONFIG_symbol .macro foo ... .endm .macro bar ... .endm .macro baz ... .endm #else .macro foo ... .endm .macro bar ... .endm #ifdef CONFIG_symbol2 .macro baz ... .endm #else .macro baz ... .endm #endif #endif such as one defintion being updated, but the other definitions miss out. Where the contents of a macro needs to be conditional, the hint is in the first clause of this very sentence. "contents" "conditional". Not multiple separate definitions, especially not when much of the macro is the same between different configs. This patch fixes this bad style, which had caused the Thumb2 code to miss-out on the uaccess updates. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: entry: provide uaccess assembly macro hooks
Provide hooks into the kernel entry and exit paths to permit control of userspace visibility to the kernel. The intended use is: - on entry to kernel from user, uaccess_disable will be called to disable userspace visibility - on exit from kernel to user, uaccess_enable will be called to enable userspace visibility - on entry from a kernel exception, uaccess_save_and_disable will be called to save the current userspace visibility setting, and disable access - on exit from a kernel exception, uaccess_restore will be called to restore the userspace visibility as it was before the exception occurred. These hooks allows us to keep userspace visibility disabled for the vast majority of the kernel, except for localised regions where we want to explicitly access userspace. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARM: software-based priviledged-no-access support
Provide a software-based implementation of the priviledged no access support found in ARMv8.1. Userspace pages are mapped using a different domain number from the kernel and IO mappings. If we switch the user domain to "no access" when we enter the kernel, we can prevent the kernel from touching userspace. However, the kernel needs to be able to access userspace via the various user accessor functions. With the wrapping in the previous patch, we can temporarily enable access when the kernel needs user access, and re-disable it afterwards. This allows us to trap non-intended accesses to userspace, eg, caused by an inadvertent dereference of the LIST_POISON* values, which, with appropriate user mappings setup, can be made to succeed. This in turn can allow use-after-free bugs to be further exploited than would otherwise be possible. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Commits on Aug 27, 2015
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cxl: Release irqs if memory allocation fails
This minor patch plugs a potential irq leak in case of a memory allocation failure inside function the afu_allocate_irqs. Presently the irqs allocated to the context gets leaked if allocation of either one of context irq_bitmap or irq_names fails. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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cxl: Remove racy attempt to force EEH invocation in reset
cxl_reset currently PERSTs the slot, and then repeatedly tries to read MMIO space in order to kick off EEH. There are 2 problems with this: it's unnecessary, and it's racy. It's unnecessary because the PERST will bring down the PHB link. That will be picked up by the CAPP, which will send out an HMI. Skiboot, noticing an HMI from the CAPP, will send an OPAL notification to the kernel, which will trigger EEH recovery. It's also racy: the EEH recovery triggered by the CAPP will eventually cause the MMIO space to have its mapping invalidated and the pointer NULLed out. This races with our attempt to read the MMIO space. This is causing OOPSes in testing. Simply drop all the attempts to force EEH detection, and trust that Skiboot will send the notification and that we'll act on it. The Skiboot code to send the EEH notification has been in Skiboot for as long as CAPP recovery has been supported, so we don't need to worry about breaking obscure setups with ancient firmware. Cc: Ryan Grimm <grimm@linux.vnet.ibm.com> Cc: stable@vger.kernel.org Fixes: 62fa19d ("cxl: Add ability to reset the card") Signed-off-by: Daniel Axtens <dja@axtens.net> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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arm64: flush FP/SIMD state correctly after execve()
When a task calls execve(), its FP/SIMD state is flushed so that none of the original program state is observeable by the incoming program. However, since this flushing consists of setting the in-memory copy of the FP/SIMD state to all zeroes, the CPU field is set to CPU 0 as well, which indicates to the lazy FP/SIMD preserve/restore code that the FP/SIMD state does not need to be reread from memory if the task is scheduled again on CPU 0 without any other tasks having entered userland (or used the FP/SIMD in kernel mode) on the same CPU in the mean time. If this happens, the FP/SIMD state of the old program will still be present in the registers when the new program starts. So set the CPU field to the invalid value of NR_CPUS when performing the flush, by calling fpsimd_flush_task_state(). Cc: <stable@vger.kernel.org> Reported-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reported-by: Janet Liu <janet.liu@spreadtrum.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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powerpc/iommu: Set default DMA offset in dma_dev_setup
Commit e91c251 "powerpc/iommu: Cleanup setting of DMA base/offset" expects that the default DMA offset is set from pnv_ioda_setup_bus_dma() which is correct unless it is SRIOV where the code flow is different - at the moment when pnv_ioda_setup_bus_dma() is called, PCI devices for VFs are not created yet. This adds missing set_dma_offset() to pnv_pci_ioda_dma_dev_setup() to cover the case of SRIOV. Note that we still need set_dma_offset() in pnv_ioda_setup_bus_dma() as at the boot time pnv_pci_ioda_dma_dev_setup() is called when no PE was created yet, this happens at the PHB fixup stage. Fixes: e91c251 ("powerpc/iommu: Cleanup setting of DMA base/offset") Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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powerpc/powernv: Enable LEDS support
Commit 84ad6e5 added LEDS support for PowerNV platform. Lets update ppc64_defconfig to pick LEDS driver. PowerNV LEDS driver looks for "/ibm,opal/leds" node in device tree and loads if this node exists. Hence added it as 'm'. Also note that powernv LEDS driver needs NEW_LEDS and LEDS_CLASS as well. Hence added them to config file. mpe: Also add them to pseries_defconfig, which is currently also used for powernv systems. Suggested-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Cc: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/…
…scottwood/linux into next Freescale updates from Scott: "Highlights include 32-bit memcpy/memset optimizations, checksum optimizations, 85xx config fragments and updates, device tree updates, e6500 fixes for non-SMP, and misc cleanup and minor fixes."
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gpio: tc3589x: use static container helper
There is a helper function to do the container_of() magic for the tc3589x GPIO, so use it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dlm: print error from kernel_sendpage
Print a dlm-specific error when a socket error occurs when sending a dlm message. Signed-off-by: Bob Peterson <rpeterso@redhat.com> Signed-off-by: David Teigland <teigland@redhat.com>
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tile: correct some typos in opcode type names
These particular opcode names are not used in the kernel directly, so updating them just has the effect of making downstream consumers more likely to end up using better names; this was reported from the qemu community. Reported-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
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Commits on Aug 28, 2015
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powerpc/pseries: Fix corrupted pdn list
Commit cca87d3 ("powerpc/pci: Refactor pci_dn") introduced pdn list for SRIOV VFs. It means the pdn is be put into the child list of its parent pdn when the pdn is created. When doing PCI hot unplugging on pSeries, the PCI device node as well as its pdn are released through procfs entry "powerpc/ofdt". Some one else grabs the memory chunk of the pdn and update it accordingly. At the same time, the pdn is still tracked in the child list of parent pdn. It leads to corrupted child list in the parent pdn. This fixes above issue by removing the pdn from the child list of its parent pdn when the device node is detached from the system. Note the pdn is free'd when the device node is released if the device node is dynamic one. Otherwise, the device node as well as the pdn won't be released. Fixes: cca87d3 ("powerpc/pci: Refactor pci_dn") Cc: stable@vger.kernel.org # 4.1+ Reported-by: Santwana Samantray <santwana.samantray@in.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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powerpc/pseries: Cleanup on pci_dn_reconfig_notifier()
This applies cleanup on pci_dn_reconfig_notifier(), no functional changes: * Rename variable "pci" to "pdn" to indicate its purpose clearly. * The parent node can be released at any time. So it should be hold with of_get_parent() before accessing it. * The device node doesn't have to have parent node in theory. More check on this. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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powerpc/eeh: Fix fenced PHB caused by eeh_slot_error_detail()
The config space of some PCI devices can't be accessed when their PEs are in frozen state. Otherwise, fenced PHB might be seen. Those PEs are identified with flag EEH_PE_CFG_RESTRICTED, meaing EEH_PE_CFG_BLOCKED is set automatically when the PE is put to frozen state (EEH_PE_ISOLATED). eeh_slot_error_detail() restores PCI device BARs with eeh_pe_restore_bars(), which then calls eeh_ops->restore_config() to reinitialize the PCI device in (OPAL) firmware. eeh_ops->restore_config() produces PCI config access that causes fenced PHB. The problem was reported on below adapter: 0001:01:00.0 0200: 14e4:168e (rev 10) 0001:01:00.0 Ethernet controller: Broadcom Corporation \ NetXtreme II BCM57810 10 Gigabit Ethernet (rev 10) This fixes the issue by skipping eeh_pe_restore_bars() in eeh_slot_error_detail() when EEH_PE_CFG_BLOCKED is set for the PE. Fixes: b6541db ("powerpc/eeh: Block PCI config access upon frozen PE") Cc: stable@vger.kernel.org # v4.0+ Reported-by: Manvanthara B. Puttashankar <mputtash@in.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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MIPS: CPS: use 32b accesses to GCRs
Commit b677bc0 ("MIPS: cps-vec: Use macros for various arithmetics and memory operations") replaced various load & store instructions through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat overzealous in doing so for CM GCR accesses, since the bit width of the CM doesn't necessarily match that of the CPU. The registers accessed (GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access using 32b instructions, so do so in order to avoid issues when using a 32b CM with a 64b CPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.16+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10864/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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f2fs: avoid accessing NULL pointer in f2fs_drop_largest_extent
If extent cache is disable, we will encounter oops when triggering direct IO as below: BUG: unable to handle kernel NULL pointer dereference at 0000000c IP: [<f0b9c61e>] f2fs_drop_largest_extent+0xe/0x30 [f2fs] *pdpt = 000000002bb9a001 *pde = 0000000000000000 Oops: 0000 [#1] SMP Modules linked in: f2fs(O) fuse bnep rfcomm bluetooth nfsd dm_crypt nfs_acl auth_rpcgss oid_registry nfs binfmt_misc fscache lockd sunrpc grace snd_intel8x0 snd_ac97_codec ac97_bus snd_pcm snd_seq_midi snd_rawmidi snd_seq_midi_event snd_seq snd_timer snd_seq_device snd soundcore joydev psmouse hid_generic i2c_piix4 serio_raw ppdev mac_hid parport_pc lp parport ext4 jbd2 mbcache usbhid hid e1000 CPU: 3 PID: 3608 Comm: dd Tainted: G O 4.2.0-rc4 #12 Hardware name: innotek GmbH VirtualBox/VirtualBox, BIOS VirtualBox 12/01/2006 task: ef161600 ti: ebd5e000 task.ti: ebd5e000 EIP: 0060:[<f0b9c61e>] EFLAGS: 00010202 CPU: 3 EIP is at f2fs_drop_largest_extent+0xe/0x30 [f2fs] EAX: 00000000 EBX: ddebc000 ECX: 00000000 EDX: 00000000 ESI: ebd5fdf8 EDI: 00000000 EBP: ebd5fd58 ESP: ebd5fd58 DS: 007b ES: 007b FS: 00d8 GS: 0033 SS: 0068 CR0: 80050033 CR2: 0000000c CR3: 2c24ee40 CR4: 000006f0 Stack: ebd5fda4 f0b8c005 00000000 00000001 00000000 f0b8c430 c816cd68 ddebc000 ddebc088 00001000 00000555 00000555 ffffffff c160bb00 00055501 00000000 00000000 00000100 00000000 ebd5fe20 f0b8c430 00000046 ef161600 00001000 Call Trace: [<f0b8c005>] __allocate_data_block+0x1a5/0x260 [f2fs] [<f0b8c430>] ? f2fs_direct_IO+0x370/0x440 [f2fs] [<c160bb00>] ? down_read+0x30/0x50 [<f0b8c430>] f2fs_direct_IO+0x370/0x440 [f2fs] [<c113e115>] generic_file_direct_write+0xa5/0x260 [<c10b53f8>] ? current_fs_time+0x18/0x50 [<c113e38b>] __generic_file_write_iter+0xbb/0x210 [<c113e50f>] ? generic_file_write_iter+0x2f/0x320 [<c113e63c>] generic_file_write_iter+0x15c/0x320 [<f0b77f29>] f2fs_file_write_iter+0x39/0x80 [f2fs] [<c11984d9>] __vfs_write+0xa9/0xe0 [<c1199227>] vfs_write+0x97/0x180 [<c119955b>] SyS_write+0x5b/0xd0 [<c160dcd0>] sysenter_do_call+0x12/0x12 Code: 10 8b 50 1c 89 53 14 eb ca 8d 74 26 00 85 f6 74 86 eb a6 0f 0b 90 8d b4 26 00 00 00 00 55 89 e5 3e 8d 74 26 00 8b 80 d4 02 00 00 <8b> 48 0c 39 d1 77 0e 03 48 14 39 ca 73 07 c7 40 14 00 00 00 00 EIP: [<f0b9c61e>] f2fs_drop_largest_extent+0xe/0x30 [f2fs] SS:ESP 0068:ebd5fd58 CR2: 000000000000000c ---[ end trace a38c07026a1afffd ]--- This is because when extent cache is disable, extent_tree pointer in struct f2fs_inode_info should be NULL, but in f2fs_drop_largest_extent we access this NULL pointer directly without checking state of extent cache, then, the oops occurs. Let's fix it by checking state of extent cache before accessing. Signed-off-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
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Commits on Aug 30, 2015
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cxl: Fix + cleanup error paths in cxl_dev_context_init
If the cxl_context_alloc() call fails, we return immediately without releasing the reference on the AFU device, allowing it to leak. This patch switches to using goto style error handling so that the device is released in common code for both error paths, and will also simplify things if we add additional initialisation in this function in the future. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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cxl: Fix force unmapping mmaps of contexts allocated through the kern…
…el api The cxl user api uses the address_space associated with the file when we need to force unmap all cxl mmap regions (e.g. on eeh, driver detach, etc). Currently, contexts allocated through the kernel api do not do this and instead skip the mmap invalidation, potentially allowing them to poke at the hardware after such an event, which may cause all sorts of trouble. This patch allocates an address_space for cxl contexts allocated through the kernel api so that the same invalidate path will for these contexts as well. We don't use the anonymous inode's address_space, as doing so could invalidate any mmaps of completely unrelated drivers using anonymous file descriptors. This patch also introduces a kernelapi flag, so we know when freeing the context if the address_space was allocated by us and needs to be freed. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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cxl: Set up and enable PSL Timebase
This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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MIPS: pgtable-bits.h: Correct _PAGE_GLOBAL_SHIFT build failure
Correct a build failure introduced by be0c37c [MIPS: Rearrange PTE bits into fixed positions.]: In file included from ./arch/mips/include/asm/io.h:27:0, from ./arch/mips/include/asm/page.h:176, from include/linux/mm_types.h:15, from include/linux/sched.h:27, from include/linux/ptrace.h:5, from arch/mips/kernel/cpu-probe.c:16: ./arch/mips/include/asm/pgtable-bits.h:164:0: error: "_PAGE_GLOBAL_SHIFT" redefined [-Werror] #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) ^ ./arch/mips/include/asm/pgtable-bits.h:141:0: note: this is the location of the previous definition #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) ^ cc1: all warnings being treated as errors make[2]: *** [arch/mips/kernel/cpu-probe.o] Error 1 for 64BIT/CPU_MIPSR1/MIPS_HUGE_TLB_SUPPORT configurations. Remove the scattered double `_PAGE_NO_EXEC_SHIFT' and `_PAGE_GLOBAL_SHIFT' macro definitions and rearrange them so that the respective macros these definitions are based on are also those used for guarding conditionals. [ralf@linux-mips.org: resolved conflicts and updated commments.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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pinctrl: at91: fix null pointer dereference
Not all gpio banks are necessarily enabled, in the current code this can lead to null pointer dereferences. [ 51.130000] Unable to handle kernel NULL pointer dereference at virtual address 00000058 [ 51.130000] pgd = dee04000 [ 51.130000] [00000058] *pgd=3f66d831, *pte=00000000, *ppte=00000000 [ 51.140000] Internal error: Oops: 17 [#1] ARM [ 51.140000] Modules linked in: [ 51.140000] CPU: 0 PID: 1664 Comm: cat Not tainted 4.1.1+ #6 [ 51.140000] Hardware name: Atmel SAMA5 [ 51.140000] task: df6dd880 ti: dec60000 task.ti: dec60000 [ 51.140000] PC is at at91_pinconf_get+0xb4/0x200 [ 51.140000] LR is at at91_pinconf_get+0xb4/0x200 [ 51.140000] pc : [<c01e71a0>] lr : [<c01e71a0>] psr: 600f0013 sp : dec61e48 ip : 600f0013 fp : df522538 [ 51.140000] r10: df52250c r9 : 00000058 r8 : 00000068 [ 51.140000] r7 : 00000000 r6 : df53c910 r5 : 00000000 r4 : dec61e7c [ 51.140000] r3 : 00000000 r2 : c06746d4 r1 : 00000000 r0 : 00000003 [ 51.140000] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 51.140000] Control: 10c53c7d Table: 3ee04059 DAC: 00000015 [ 51.140000] Process cat (pid: 1664, stack limit = 0xdec60208) [ 51.140000] Stack: (0xdec61e48 to 0xdec62000) [ 51.140000] 1e40: 00000358 00000000 df522500 ded15f80 c05a9d08 ded15f80 [ 51.140000] 1e60: 0000048c 00000061 df522500 ded15f80 c05a9d08 c01e7304 ded15f80 00000000 [ 51.140000] 1e80: c01e6008 00000060 0000048c c01e6034 c01e5f6c ded15f80 dec61ec 00000000 [ 51.140000] 1ea0: 00020000 ded6f280 dec61f80 00000001 00000001 c00ae0b8 b6e80000 ded15fb0 [ 51.140000] 1ec0: 00000000 00000000 df4bc974 00000055 00000800 ded6f280 b6e80000 ded6f280 [ 51.140000] 1ee0: ded6f280 00020000 b6e80000 00000000 00020000 c0090dec c0671e1c dec61fb0 [ 51.140000] 1f00: b6f8b510 00000001 00004201 c000924c 00000000 00000003 00000003 00000000 [ 51.140000] 1f20: df4bc940 00022000 00000022 c066e188 b6e7f000 c00836f4 000b6e7f ded6f280 [ 51.140000] 1f40: ded6f280 b6e80000 dec61f80 ded6f280 00020000 c0091508 00000000 00000003 [ 51.140000] 1f60: 00022000 00000000 00000000 ded6f280 ded6f280 00020000 b6e80000 c0091d9c [ 51.140000] 1f80: 00000000 00000000 ffffffff 00020000 00020000 b6e80000 00000003 c000f124 [ 51.140000] 1fa0: dec60000 c000efa0 00020000 00020000 00000003 b6e80000 00020000 000271c4 [ 51.140000] 1fc0: 00020000 00020000 b6e80000 00000003 7fffe000 00000000 00000000 00020000 [ 51.140000] 1fe0: 00000000 bef50b64 00013835 b6f29c76 400f0030 00000003 00000000 00000000 [ 51.140000] [<c01e71a0>] (at91_pinconf_get) from [<c01e7304>] (at91_pinconf_dbg_show+0x18/0x2c0) [ 51.140000] [<c01e7304>] (at91_pinconf_dbg_show) from [<c01e6034>] (pinconf_pins_show+0xc8/0xf8) [ 51.140000] [<c01e6034>] (pinconf_pins_show) from [<c00ae0b8>] (seq_read+0x1a0/0x464) [ 51.140000] [<c00ae0b8>] (seq_read) from [<c0090dec>] (__vfs_read+0x20/0xd0) [ 51.140000] [<c0090dec>] (__vfs_read) from [<c0091508>] (vfs_read+0x7c/0x108) [ 51.140000] [<c0091508>] (vfs_read) from [<c0091d9c>] (SyS_read+0x40/0x94) [ 51.140000] [<c0091d9c>] (SyS_read) from [<c000efa0>] (ret_fast_syscall+0x0/0x3c) [ 51.140000] Code: eb010ec2 e30a0d08 e34c005a eb0ae5a7 (e5993000) [ 51.150000] ---[ end trace fb3c370da3ea4794 ]--- Fixes: a0b957f ("pinctrl: at91: allow to have disabled gpio bank") Cc: stable@vger.kernel.org # 3.18 Signed-off-by: David Dueck <davidcdueck@googlemail.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Commits on Aug 31, 2015
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Revert "gpio: extraxfs: fix returnvar.cocci warnings"
This reverts commit 5e22ec0.
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perf tools: Fix build on powerpc broken by pt/bts
It is theoretically possible to process perf.data files created on x86 and that contain Intel PT or Intel BTS data, on any other architecture, which is why it is possible for there to be build errors on powerpc caused by pt/bts. The errors were: util/intel-pt-decoder/intel-pt-insn-decoder.c: In function ‘intel_pt_insn_decoder’: util/intel-pt-decoder/intel-pt-insn-decoder.c:138:3: error: switch missing default case [-Werror=switch-default] switch (insn->immediate.nbytes) { ^ cc1: all warnings being treated as errors linux-acme.git/tools/perf/perf-obj/libperf.a(libperf-in.o): In function `intel_pt_synth_branch_sample': sources/linux-acme.git/tools/perf/util/intel-pt.c:871: undefined reference to `tsc_to_perf_time' linux-acme.git/tools/perf/perf-obj/libperf.a(libperf-in.o): In function `intel_pt_sample': sources/linux-acme.git/tools/perf/util/intel-pt.c:915: undefined reference to `tsc_to_perf_time' sources/linux-acme.git/tools/perf/util/intel-pt.c:962: undefined reference to `tsc_to_perf_time' linux-acme.git/tools/perf/perf-obj/libperf.a(libperf-in.o): In function `intel_pt_process_event': sources/linux-acme.git/tools/perf/util/intel-pt.c:1454: undefined reference to `perf_time_to_tsc' Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Cc: Wang Nan <wangnan0@huawei.com> Cc: Zefan Li <lizefan@huawei.com> Cc: pi3orama@163.com Link: http://lkml.kernel.org/r/1441046384-28663-1-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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bpf tools: New API to get name from a BPF object
Before this patch there's no way to connect a loaded bpf object to its source file. However, during applying perf's '--filter' to BPF object, without this connection makes things harder, because perf loads all programs together, but '--filter' setting is for each object. The API of bpf_object__open_buffer() is changed to allow passing a name. Fortunately, at this time there's only one user of it (perf test LLVM), so we change it together. Signed-off-by: Wang Nan <wangnan0@huawei.com> Cc: Alexei Starovoitov <ast@plumgrid.com> Cc: Brendan Gregg <brendan.d.gregg@gmail.com> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: David Ahern <dsahern@gmail.com> Cc: He Kuang <hekuang@huawei.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kaixu Xia <xiakaixu@huawei.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Zefan Li <lizefan@huawei.com> Cc: pi3orama@163.com Link: http://lkml.kernel.org/r/1440742821-44548-2-git-send-email-wangnan0@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf evlist: Open event on evsel cpus and threads
An evsel may have different cpus and threads than the evlist it is in. Use it's own cpus and threads, when opening the evsel in 'perf record'. Signed-off-by: Kan Liang <kan.liang@intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Link: http://lkml.kernel.org/r/1440138194-17001-1-git-send-email-kan.liang@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf script: Enable printing of interrupted machine state
This patch adds the output of the interrupted machine state (iregs) to perf script. It presents them as NAME:VALUE so this is easy to parse during post processing. To capture the interrupted machine state: $ perf record -I .... to display iregs, use the -F option: $ perf script -F ip,iregs 40afc2 AX:0x6c5770 BX:0x1e CX:0x5f4d80a DX:0x101010101010101 SI:0x1 Signed-off-by: Stephane Eranian <eranian@google.com> Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1441039273-16260-2-git-send-email-eranian@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf/x86: Add list of register names
This patch adds a way to locate a register identifier (PERF_X86_REG_*) based on its name, e.g., AX. This will be used by a subsequent patch to improved flexibility of perf record. Signed-off-by: Stephane Eranian <eranian@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1441039273-16260-3-git-send-email-eranian@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf record: Add ability to name registers to record
This patch modifies the -I/--int-regs option to enablepassing the name of the registers to sample on interrupt. Registers can be specified by their symbolic names. For instance on x86, --intr-regs=ax,si. The motivation is to reduce the size of the perf.data file and the overhead of sampling by only collecting the registers useful to a specific analysis. For instance, for value profiling, sampling only the registers used to passed arguements to functions. With no parameter, the --intr-regs still records all possible registers based on the architecture. To name registers, it is necessary to use the long form of the option, i.e., --intr-regs: $ perf record --intr-regs=si,di,r8,r9 ..... To record any possible registers: $ perf record -I ..... $ perf report --intr-regs ... To display the register, one can use perf report -D To list the available registers: $ perf record --intr-regs=\? available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10 R11 R12 R13 R14 R15 Signed-off-by: Stephane Eranian <eranian@google.com> Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1441039273-16260-4-git-send-email-eranian@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux…
…/kernel/git/acme/linux into perf/urgent Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo: User visible changes: - Add ability to specify to select which registers to record, to reduce the size of perf.data files, and also allow printing the registers in 'perf script': (Stephane Eranian) # perf record --intr-regs=AX,SP usleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.016 MB perf.data (8 samples) ] # perf script -F ip,sym,iregs | tail -5 ffffffff8105f42a native_write_msr_safe AX:0xf SP:0xffff8802629c3c00 ffffffff8105f42a native_write_msr_safe AX:0xf SP:0xffff8802629c3c00 ffffffff81761ac0 _raw_spin_lock AX:0xffff8801bfcf8020 SP:0xffff8802629c3ce8 ffffffff81202bf8 __vma_adjust_trans_huge AX:0x7ffc75200000 SP:0xffff8802629c3b30 ffffffff8122b089 dput AX:0x101 SP:0xffff8802629c3c78 # Infrastructure changes: - Open event on evsel cpus and threads. (Kan Liang) - Add new bpf API to get name from a BPF object. (Wang Nan) Build fixes: - Fix build on powerpc broken by pt/bts. (Adrian Hunter) Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
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perf dwarf: Fix potential array out of bounds access
There is a problem in the dwarf-regs.c files for sh, sparc and x86 where it is possible to make an out-of-bounds array access when searching for register names. This patch fixes it by replacing '<=' to '<', so when register (number == XXX_MAX_REGS), get_arch_regstr() will return NULL. Signed-off-by: Wang Nan <wangnan0@huawei.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Acked-by: Jiri Olsa <jolsa@kernel.org> Acked-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: David S. Miller <davem@davemloft.net> Cc: Zefan Li <lizefan@huawei.com> Cc: pi3orama@huawei.com Link: http://lkml.kernel.org/r/1441078184-105038-1-git-send-email-wangnan0@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf build: Fix Intel PT instruction decoder dependency problem
I hit following building error randomly: ... /bin/sh: /path/to/kernel/buildperf/util/intel-pt-decoder/inat-tables.c: No such file or directory ... LINK /path/to/kernel/buildperf/plugin_mac80211.so LINK /path/to/kernel/buildperf/plugin_kmem.so LINK /path/to/kernel/buildperf/plugin_xen.so LINK /path/to/kernel/buildperf/plugin_hrtimer.so In file included from util/intel-pt-decoder/intel-pt-insn-decoder.c:25:0: util/intel-pt-decoder/inat.c:24:25: fatal error: inat-tables.c: No such file or directory #include "inat-tables.c" ^ compilation terminated. make[4]: *** [/path/to/kernel/buildperf/util/intel-pt-decoder/intel-pt-insn-decoder.o] Error 1 make[4]: *** Waiting for unfinished jobs.... LINK /path/to/kernel/buildperf/plugin_function.so This is caused by tools/perf/util/intel-pt-decoder/Build that, it tries to generate $(OUTPUT)util/intel-pt-decoder/inat-tables.c atomatically but forget to ensure the existance of $(OUTPUT)util/intel-pt-decoder directory. This patch fixes it by adding $(call rule_mkdir) like other similar rules. Signed-off-by: Wang Nan <wangnan0@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Jiri Olsa <jolsa@kernel.org> Cc: Zefan Li <lizefan@huawei.com> Cc: pi3orama@163.com Link: http://lkml.kernel.org/r/1441087005-107540-1-git-send-email-wangnan0@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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perf tools: Fix link time error with sample_reg_masks on non x86
This patch makes perf compile on non x86 platforms by defining a weak symbol for sample_reg_masks[] in util/perf_regs.c. The patch also moves the REG() and REG_END() macros into the util/per_regs.h header file. The macros are renamed to SMPL_REG/SMPL_REG_END to avoid clashes with other header files. Signed-off-by: Stephane Eranian <eranian@google.com> Acked-by: Jiri Olsa <jolsa@kernel.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: David Ahern <dsahern@gmail.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1441099814-26783-1-git-send-email-eranian@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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f2fs: upset segment_info repair
upset segment_info like this: 276000|161 0|0 4|70 3|0 3|0 0|0 0|91 4|0 4|232 4|39 276104|0 4|0 4|1 4|0 4|0 4|280 4|0 4|42 4|262 4|38 276204|179 4|89 4|39 4|24 4|0 4|96 4|3 4|428 4|0 4|118 276304|112 4|97 4|0 4|0 4|0 4|68 4|0 4|0 4|86 4|138 276404|0 4|0 0|166 5|39 4|101 0|111 Signed-off-by: Yunlei He <heyunlei@huawei.com> Reviewed-by: Chao Yu <chao2.yu@samsung.com> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Yunlei He authored and Jaegeuk Kim committedSep 1, 2015 Configuration menu - View commit details
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Commits on Sep 2, 2015
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Merge tag 'perf-urgent-for-mingo' of git://git.kernel.org/pub/scm/lin…
…ux/kernel/git/acme/linux into perf/urgent Pull perf/urgent fixes from Arnaldo Carvalho de Melo: - Fix link time error with sample_reg_masks on non-x86. (Stephane Eranian) - Fix potential array out of bounds access. (Wang Nan) - Fix Intel PT instruction decoder dependency problem. (Wang Nan) Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
Ingo Molnar committedSep 2, 2015 Configuration menu - View commit details
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Commits on Sep 3, 2015
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MIPS: Remove "weak" from get_c0_compare_int() declaration
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). get_c0_compare_int() is defined in several files. Each definition is weak, so I assume Kconfig prevents two or more from being included. The caller contains default code used when get_c0_compare_int() isn't defined at all. Add a weak get_c0_compare_int() definition with the default code and remove the weak annotation from the declaration. Then the platform implementations will be strong and will override the weak default. If multiple platforms are ever configured in, we'll get a link error instead of calling a random platform's implementation. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove "weak" from get_c0_fdc_int() declaration
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). The most elegant solution is to have a weak default implementation and allow a strong function to override it. Then we don't have to test whether a definition is present, and if there are ever multiple strong definitions, we get a link error instead of calling a random definition. Add a weak get_c0_fdc_int() definition with the default code and remove the weak annotation from the declaration. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10687/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove "weak" from mips_cdmm_phys_base() declaration
Weak header file declarations are error-prone because they make every definition weak, and the linker chooses one based on link order (see 10629d7 ("PCI: Remove __weak annotation from pcibios_get_phb_of_node decl")). mips_cdmm_phys_base() is defined only in arch/mips/mti-malta/malta-memory.c so there's no problem with multiple definitions. But it works better to have a weak default implementation and allow a strong function to override it. Then we don't have to test whether a definition is present, and if there are ever multiple strong definitions, we get a link error instead of calling a random definition. Add a weak mips_cdmm_phys_base() definition and remove the weak annotation from the declaration in arch/mips/include/asm/cdmm.h. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10688/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove "__weak" definition from arch-specific linkage.h
"__weak" is defined in include/linux/compiler-gcc.h. We shouldn't need an arch-specific definition. Remove the "__weak" definition from arch/mips/include/asm/linkage.h. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10689/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Declare MSA MI10 instruction formats
Declare a struct describing the MSA MI10 instruction format used for ld & st instructions, for use by subsequent patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10571/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Introduce accessors for MSA vector registers
Introduce accessor functions allowing the kernel to access arbitrary vector registers using an arbitrary data format. The accessors are implemented in assembly, using macros to avoid massive duplication, in order to make use of the existing support for MSA with & without toolchain support. The accessors will be used in a later patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10572/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: MSA unaligned memory access support
The MSA architecture specification allows for hardware to not implement unaligned vector memory accesses in some or all cases. A typical example of this is the I6400 core which does not implement unaligned vector memory access when the memory crosses a page boundary. The architecture also requires that such memory accesses complete successfully as far as userland is concerned, so the kernel is required to emulate them. This patch implements support for emulating unaligned MSA ld & st instructions by copying between the user memory & the tasks FP context in struct thread_struct, updating hardware registers from there as appropriate in order to avoid saving & restoring the entire vector context for each unaligned memory access. Tested both using an I6400 CPU and with a QEMU build hacked to produce AdEL exceptions for unaligned vector memory accesses. [paul.burton@imgtec.com: - Remove #ifdef's - Move msa_op into enum major_op rather than #define - Replace msa_{to,from}_wd with {read,write}_msa_wr_{b,h,w,l} and the format-agnostic wrappers, removing the custom endian mangling for big endian systems. - Restructure the msa_op case in emulate_load_store_insn to share more code between the load & store cases. - Avoid the need for a temporary union fpureg on the stack by simply reusing the already suitably aligned context in struct thread_struct. - Use sizeof(*fpr) rather than hardcoding 16 as the size for user memory checks & copies. - Stop recalculating the address of the unaligned vector memory access and rely upon the value read from BadVAddr as we do for other unaligned memory access instructions. - Drop the now unused val8 & val16 fields in union fpureg. - Rewrite commit message. - General formatting cleanups.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Jie Chen <chenj@lemote.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10573/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: mm: default platform_maar_init using bootmem data
Introduce a default weak implementation of platform_maar_init which makes use of the data that platforms already provide to the bootmem allocator. This should hopefully cover the most common configurations, reduce the duplication of information provided by platforms & leaves platforms with the option of providing a custom implementation if required. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Patchwork: https://patchwork.linux-mips.org/patch/10676/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: malta: Use generic platform_maar_init
The default implementation of platform_maar_init is sufficient for Malta boards where we want to allow speculation in the regions of memory corresponding to DDR & disallow it elsewhere. Drop the custom implementation such that the default is used, reducing the duplication of information provided by the Malta platform code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10677/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Use unsigned int when reading CP0 registers
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There is little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. This has come up via u-boot[1] which sync's asm/mipsregs.h with the kernel. In u-boots case the value read from read_c0_count() is assigned to an unsigned long [2] which triggers a sign extension and causes a bug. U-boot should probably be more explicit about the types used for the timer_read_counter() API but that aside is there any reason to treat these values as signed integers? A quick grep around the arch/mips makes me thing that there may be some bugs lurking when read_c0_count() starts to yield a negative value but I haven't really explored any of them. [1] - http://lists.denx.de/pipermail/u-boot/2015-July/219086.html [2] - http://git.denx.de/?p=u-boot.git;a=blob;f=arch/mips/cpu/time.c#l11 Signed-off-by: Chris Packham <judge.packham@gmail.com> Cc: linux-mips@linux-mips.org Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Chris Packham <judge.packham@gmail.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10718/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Treat CP1 control registers as unsigned ints.
These are bitfields and treating them as signed values doesn't make any sense. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Chris Packham <judge.packham@gmail.com>
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MIPS: Kconfig: Drop the EXPERIMENTAL tag from MIPS R6
The MIPS R6 ISA support has been part of mainline since v4.0 and it should be in a good shape nowadays so it is not an experimental feature anymore. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cp1emu: Fix closing bracket for the d_fmt case
The double format (d_fmt) case uses an opening bracket which then closes at the end of the word format (w_fmt). This can be rather confusing so add the closing bracket at the end of the d_fmt case and use another one for the w_fmt one. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10733/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Fix indentation
Fix indentation for the final 'else' blocks. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10735/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Allow m{f,t}hc emulation on MIPS R6
The mfhc/mthc instructions are supported on MIPS R6 so emulate them if needed. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10737/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions
Commit c8a3458 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") added support for emulating the new R6 BC1{EQ,NE}Z branches but it missed the case where the instruction that caused the exception was not on a DS. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: c8a3458 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") Cc: <stable@vger.kernel.org> # 4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10738/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Documentation/sysrq.txt: Mention MIPS TLB dump (x)
Commit d1e9a4f ("MIPS: Add SysRq operation to dump TLBs on all CPUs") added the 'x' sysrq key for dumping MIPS TLB entries, but didn't document it in Documentation/sysrq.txt. Add mention of the MIPS use of the 'x' SysRq key. Reported-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Jonathan Corbet <corbet@lwn.net> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-doc@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Refactor dumping of TLB registers for r3k/r4k
The TLB registers are dumped in a couble of places: - sysrq_tlbdump_single() - when dumping TLB state. - do_mcheck() - in response to a machine check error. The main TLB registers also differ between r3k and r4k, but r4k appears to be assumed. Refactor this code into a dump_tlb_regs() function, implemented for both r3k and r4k, and used by both of the above functions. Fixes: d1e9a4f ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10721/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Probe for small (1KiB) page support
Probe Config3 for small page support. This will be useful to give clues as to whether the PageGrain register exists. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10722/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: dump_tlb: Only dump PageGrain if interesting
The PageGrain register may not exist if certain architectural features aren't present, therefore only print out its value when dumping the TLB registers if it is expected to contain fields relevant to the TLB. Fixes: d1e9a4f ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Reported-by: Joshua Kinard <kumba@gentoo.org> Reported-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: dump_tlb: Dump FrameMask register if exists
The FrameMask register is relevant to the TLB so it should be dumped by dump_tlb_regs(), however it is only present in certain cores (r10000, r12000, r14000, r16000). Add dumping of it, conditional upon current_cpu_type(). Suggested-by: Joshua Kinard <kumba@gentoo.org> Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10724/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Rearrange ENTRYLO field definitions
The generic field definitions (i.e. present before MIPS32/MIPS64) in mipsregs.h are conventionally not prefixed with MIPS_, so rename the recently added MIPS_ENTRYLO_* definitions for the G, V, D, and C fields to ENTRYLO_*. Also rearrange to put the EntryLo and EntryHi definitions in the right place in the file. Fixes: 8ab6abc ("MIPS: mipsregs.h: Add EntryLo bit definitions") Reported-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Sibyte: Move bus watcher from deprecated __initcall to device_i…
…nitcall Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: unaligned: Move from deprecated __initcall to arch_initcall.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Lasat: Move from deprecated __initcall to arch_initcall.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Move from deprecated __initcall to arch_initcall.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Kconfig: Separate 32BIT and 64BIT config block by blank line.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Alchemy: Migrate to new 'set-state' interface
Migrate alchemy driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything in the ->set_mode() callback. So, this patch doesn't provide any set-state callbacks. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10599/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Jazz: Migrate to new 'set-state' interface
Migrate jazz driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything in the ->set_mode() callback. So, this patch doesn't provide any set-state callbacks. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10600/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: jz4740: Migrate to new 'set-state' interface
Migrate jz4740 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10601/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-bcm1480: Migrate to new 'set-state' interface
Migrate cevt-bcm1480 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Read operation on R_SCD_TIMER_CFG and R_SCD_TIMER_INIT registers isn't performed now for many modes as there returned values aren't used. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10602/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-ds1287: Migrate to new 'set-state' interface
Migrate cevt-ds1287 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10603/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-gt641xx: Migrate to new 'set-state' interface
Migrate cevt-gt641xx driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10604/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-r4k: Migrate to new 'set-state' interface
Migrate cevt-4k driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything in the ->set_mode() callback. So, this patch doesn't provide any set-state callbacks. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10605/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-sb1250: Migrate to new 'set-state' interface
Migrate cevt-rsb1250 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10606/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: cevt-txx9: Migrate to new 'set-state' interface
Migrate cevt-txx9 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Patchwork: https://patchwork.linux-mips.org/patch/10607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: loongson64/timer: Migrate to new 'set-state' interface
Migrate loongson driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. [ralf@linux-mips.org: Folded in Viresh's followon fix.] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Michael Opdenacker <michael.opdenacker@free-electrons.com> Cc: Hongliang Tao <taohl@lemote.com> Cc: Valentin Rothberg <valentinrothberg@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Patchwork: https://patchwork.linux-mips.org/patch/10608/ Patchwork: https://patchwork.linux-mips.org/patch/10883/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: loongsoon32: Migrate to new 'set-state' interface
Migrate loongsoon32 driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10609/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: rt3352: Migrate to new 'set-state' interface
Migrate ralink driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10610/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: IP27: Migrate to new 'set-state' interface
Migrate sgidriver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything in the ->set_mode() callback. So, this patch doesn't provide any set-state callbacks. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10611/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: sni: Migrate to new 'set-state' interface
Migrate sni driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linaro-kernel@lists.linaro.org Cc: Thomas Gleixner <tglx@linutronix.de> Patchwork: https://patchwork.linux-mips.org/patch/10612/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Simplify EVA FP context handling code
The protected_{save,restore}_fp_context functions had effectively different implementations for EVA. Simplify & unify the code somewhat such that EVA configurations simply guarantee the FPU-not-owned path through the standard code path. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10787/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add offsets to sigcontext FP fields to struct mips_abi
Add fields to struct mips_abi, which holds information regarding the kernel-userland ABI regarding signals, to specify the offsets to the FP related fields within the appropriate variant of struct sigcontext. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10788/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Use struct mips_abi offsets to save FP context
When saving FP state to struct sigcontext, make use of the offsets provided by struct mips_abi to obtain appropriate addresses for the sc_fpregs & sc_fpc_csr fields of the sigcontext. This is done only for the native struct sigcontext in this patch (ie. for O32 in CONFIG_32BIT kernels or for N64 in CONFIG_64BIT kernels) but is done in preparation for sharing this code with compat ABIs in further patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10789/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Move FP usage checks into protected_{save, restore}_fp_context
In preparation for sharing protected_{save,restore}_fp_context with compat ABIs, move the FP usage checks into said functions. This will both enable that code to be shared, and allow for extensions of it in further patches to also be shared. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Skip odd double FP registers when copying FP32 sigcontext
When a task uses 32 bit floating point, the odd indexed 32b register values are stored in bits 63:32 of the preceding even indexed 64b FP register field in saved context. Thus there is no point in preserving the odd indexed 64b register fields since they hold no valid context. This patch will cause them to be skipped, as is already done in arch/mips/kernel/signal32.c. [ralf@linux-mips.org: Fixed reject.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Maciej W. Rozycki <macro@codesourcery.com> Cc: Andrew Morton <akpm@linux-foundation.org> Patchwork: https://patchwork.linux-mips.org/patch/10791/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Use common FP sigcontext code for O32 compat
Make use of the common FP sigcontext code for O32 binaries running on MIPS64 kernels now that it is taking appropriate offsets into struct sigcontext(32) from struct mips_abi. [ralf@linux-mips.org: Fixed reject.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10792/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove unused {get,put}_sigset functions
These functions are never called & thus dead code. Remove them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Andrew Morton <akpm@linux-foundation.org> Patchwork: https://patchwork.linux-mips.org/patch/10793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Indicate FP mode in sigcontext sc_used_math
The sc_used_math field of struct sigcontext & its variants has traditionally been used as a boolean value indicating only whether or not floating point context is saved within the sigcontext. With various supported FP modes & the ability to switch between them this information will no longer be enough to decode the meaning of the data stored in the sc_fpregs fields of struct sigcontext. To make that possible 3 bits are defined within sc_used_math: - Bit 0 (USED_FP) represents whether FP was used, essentially providing the boolean flag which sc_used_math as a whole provided previously. - Bit 1 (USED_FR1) provides the value of the Status.FR bit at the time the FP context was saved. - Bit 2 (USED_HYBRID_FPRS) indicates whether the FP context was saved under the hybrid FPR scheme. Essentially, when set the odd singles are located in bits 63:32 of the preceding even indexed sc_fpregs element. Any userland that tests whether the sc_used_math field is zero or non-zero will continue to function as expected. Having said that, I could not find any userland which uses the sc_used_math field at all. [ralf@linux-mips.org: Fixed rejects.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10794/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add definitions for extended context
The context introduced by MSA needs to be saved around signals. However, we can't increase the size of struct sigcontext because that will change the offset of the signal mask in struct sigframe or struct ucontext. This patch instead places the new context immediately after the struct sigframe for traditional signals, or similarly after struct ucontext for RT signals. The layout of struct sigframe & struct ucontext is identical from their sigcontext fields onwards, so the offset from the sigcontext to the extended context will always be the same regardless of the type of signal. Userland will be able to search through the extended context by using the magic values to detect which types of context are present. Any unrecognised context can be skipped over using the size field of struct extcontext. Once the magic value END_EXTCONTEXT_MAGIC is seen it is known that there are no further extended context structures to examine. This approach is somewhat similar to that taken by ARM to save VFP & other context at the end of struct ucontext. Userland can determine whether extended context is present by checking for the USED_EXTCONTEXT bit in the sc_used_math field of struct sigcontext. Whilst this could potentially change the historic semantics of sc_used_math if further extended context which does not imply FP context were to be introduced in the future, I have been unable to find any userland code making use of sc_used_math at all. Using one of the fields described as unused in struct sigcontext was considered, but the kernel does not already write to those fields so there would be no guarantee of the field being clear on older kernels. Other alternatives would be to have userland check the kernel version, or to have a HWCAP bit indicating presence of extended context. However there is a desire to have the context & information required to decode it be self contained such that, for example, debuggers could decode the saved context easily. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Alex Smith <alex@alex-smith.me.uk> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Daniel Borkmann <dborkman@redhat.com> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10795/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Save MSA extended context around signals
It is desirable for signal handlers to be allowed to make use of MSA, particularly if auto vectorisation is used when compiling a program. The MSA context must therefore be saved & restored before & after invoking the signal handler. Make use of the extended context structs defined in the preceding patch to save MSA context after the sigframe when appropriate. [ralf@linux-mips.org: Fixed conflicts.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Richard Weinberger <richard@nod.at> Cc: James Hogan <james.hogan@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Maciej W. Rozycki <macro@codesourcery.com> Patchwork: https://patchwork.linux-mips.org/patch/10796/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: AT_HWCAP aux vector infrastructure
In order for userland to determine whether various features are safe to use, it will need to know both that the hardware supports those features and that the kernel is recent enough & configured appropriately to support them. For example under the O32 modeless FP proposal the dynamic linker & ifunc resolvers will need this information. The kernel is the only thing in a position to know availability accurately, so the kernel needs to provide the information to userland. This patch introduces the infrastructure to provide the AT_HWCAP aux vector to userland in order to provide that information. It also defines the 2 currently specified flags, which indicate MIPSr6 & MSA support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Kees Cook <keescook@chromium.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Alex Smith <alex@alex-smith.me.uk> Cc: linux-kernel@vger.kernel.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Ingo Molnar <mingo@kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/10797/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Advertise MIPSr6 via HWCAP when appropriate
When running on a CPU implementing the release 6 of the MIPS32 or MIPS64 ISA, advertise that to userland via the appropriate HWCAP bit. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10798/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Advertise MSA support via HWCAP when present
If MSA is supported by both the hardware & the kernel then advertise that support to userland via the AT_HWCAP aux vector. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10799/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Drop EXPERIMENTAL tag from O32+FP64 & MSA
CONFIG_MIPS_O32_FP64_SUPPORT and CONFIG_CPU_HAS_MSA are in pretty good shape these days, and in much wider use than they once were. Stop referring to them as EXPERIMENTAL. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Guenter Roeck <linux@roeck-us.net> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Fix definition of pgprot_writecombine()
If pgprot_writecombine is not #defined, asm-generic/pgtable.h will try to provide a default implementation by #defining it to pgprot_noncached. However our implementation is an inline function rather than a #define, so it was never actually used because of the #define in generic code. Add "#define pgprot_writecombine pgprot_writecombine" to prevent generic code from re-defining it. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10767/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Add implementation of dma_map_ops.mmap()
The generic implementation of dma_map_ops.mmap(), dma_common_mmap(), is not correct for non-coherent devices. It expects to be passed a virtual address previously returned by dma_alloc_coherent(), which for a non-coherent device will return a KSEG1 address. It then attempts to convert that virtual address to a physical address using virt_to_page() which will yield an incorrect address. Also, dma_common_mmap() does not handle the DMA_ATTR_WRITE_COMBINE attribute, and therefore dma_mmap_writecombine() will not actually set the appropriate pgprot_t flags for write combining. This patch adds an implementation of dma_map_ops.mmap() that correctly handles KSEG1 addresses, and enables write combining when requested. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Sadegh Abbasi <Sadegh.Abbasi@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Use Ingenic-specific write combine attribute on all Ingenic pla…
…tforms The Ingenic-specific write combining cache attribute was defined based on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10769/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Get rid of finish_arch_switch().
MIPS was using finish_arch_switch() as a hook to restore and initialize CPU context for all threads, even newly created kernel and user threads. This is however entirely solvable within switch_to() so get rid of finish_arch_switch() which is in the way of scheduler cleanups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Select CONFIG_ARCH_USE_CMPXCHG_LOCKREF for MIPS64
On MIPS64 we have spinlocks that are 32b in size and an efficient cmpxchg64 implementation, so we qualify to make use of cmpxchg backed lockrefs. Select the ARCH_USE_CMPXCHG_LOCKREF Kconfig symbol and provide a trivial implementation of arch_spin_value_unlocked to satisfy the lockref code. Using Linus' simple testcase from http://article.gmane.org/gmane.linux.file-systems/77466 on a dual core system with an in-development MIPS64 CPU running on FPGA I see around an 8% gain: Pre-patch: Total loops: 252698 Total loops: 251482 Total loops: 250806 Total loops: 252885 Total loops: 251666 Post-patch: Total loops: 273728 Total loops: 269932 Total loops: 269341 Total loops: 275004 Total loops: 270208 [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Maciej W. Rozycki <macro@codesourcery.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Ath79: Remove the unused GPIO function API
To prepare moving the GPIO driver to drivers/gpio remove the platform specific pinmux API. As it is not used by any board, and such functionality should better be implemented using the pinmux subsystem just removing it seems to be the best option. Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: ath79: Move the GPIO driver to drivers/gpio
GPIO drivers should be in drivers/gpio Signed-off-by: Alban Bedel <albeu@free.fr> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10597/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Remove all the uses of custom gpio.h
Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS machines, and each machine type provides its own gpio.h. However only a handful really implement the GPIO API, most just forward everythings to gpiolib. The Alchemy machine is notable as it provides a system to allow implementing the GPIO API at the board level. But it is not used by any board currently supported, so it can also be removed. For most machine types we can just remove the custom gpio.h, as well as the custom wrappers if some exists. Some of the code found in the wrappers must be moved to the respective GPIO driver. A few more fixes are need in some drivers as they rely on linux/gpio.h to provides some machine specific definitions, or used asm/gpio.h instead of linux/gpio.h for the gpio API. Signed-off-by: Alban Bedel <albeu@free.fr> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Tejun Heo <tj@kernel.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Florian Fainelli <florian@openwrt.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Joe Perches <joe@perches.com> Cc: Daniel Walter <dwalter@google.com> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Varka Bhadram <varkabhadram@gmail.com> Cc: Masanari Iida <standby24x7@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Michael Buesch <m@bues.ch> Cc: abdoulaye berthe <berthe.ab@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-ide@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-input@vger.kernel.org Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10828/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Netlogic: Use chip_data for irq_chip methods
Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data to store interrupt controller data pointer. It uses handler_data now, and that causes errors when an API (like the GPIO subsystem) tries to use the handler data. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Netlogic: add device tree entry for XLP GPIO
Add GPIO entries to the Netlogic XLP device tree files. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Netlogic: set ARCH_REQUIRE_GPIOLIB for XLP platform
This is needed to enable GPIO framework support for Netlogic XLP platform. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10818/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Netlogic: NAND IRQ mapping
Add NAND IRQ mapping for XLP9xx processor. Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10820/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Set trap_no field in thread_struct on exception.
This reverts commit 7281cd2 and adds actual functionality to use the field.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Documentation: MIPS now supports uprobes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Netlogic: Fix 0x0x prefixes.
Fix the 0x0x prefix in integer constants, in this case the registers interval is actually 0x8065 .. 0x80A4 as confirmed some lines above in the code. Signed-off-by: Antonio Ospite <ao2@ao2.it> Cc: linux-mips@linux-mips.org Cc: Jiri Kosina <trivial@kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/9908/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Tidy up FPU context switching
Rather than saving the scalar FP or vector context in the assembly resume function, reuse the existing C code we have in fpu.h to do exactly that. This reduces duplication, results in a much easier to read resume function & should allow the compiler to optimise out more MSA code due to is_msa_enabled()/cpu_has_msa being known-zero at compile time for kernels without MSA support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10830/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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CLOCKSOURCE: mips-gic: Enable the clock before using it
For the clock to be used (e.g. get its rate through clk_get_rate) it should be prepared and enabled first. Also, while the clock is enabled the driver must hold a reference to it, so let's remove the call to clk_put. Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10779/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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CLOCKSOURCE: mips-gic: Add missing error returns checks
This commit adds the required checks on the functions that return an error. Some of them are not critical, so only a warning is printed. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10780/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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CLOCKSOURCE: mips-gic: Split clocksource and clockevent initialization
This is preparation work for the introduction of clockevent frequency update with a clock notifier. This is only possible when the device is passed a clk struct, so let's split the legacy and devicetree initialization. Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Kconfig: Enable common clock framework for Malta and SEAD3
Now that we're ready to enable COMMON_CLK for GIC platforms do so for Malta and SEAD3. The only other user of the GIC Pistachio does already do so. [ralf@linux-mips.org: Rewrite the commit message because applied in the right order there is no breakage thus no fix required.] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11038/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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CLOCKSOURCE: mips-gic: Update clockevent frequency on clock rate changes
This commit introduces the clockevent frequency update, using a clock notifier. It will be used to support CPUFreq on platforms using MIPS GIC based clockevents. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10782/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Documentation: dt: Add Pistachio SoC general purpose timer binding do…
…cument Add a device-tree binding document for the clocksource driver provided by Pistachio SoC general purpose timers. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Patchwork: https://patchwork.linux-mips.org/patch/10783/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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CLOCKSOURCE: Add Pistachio clocksource-only driver
The Pistachio SoC provides four general purpose timers, and allow to implement a clocksource driver. This driver can be used as a replacement for the MIPS GIC and MIPS R4K clocksources and sched clocks, which are clocked from the CPU clock. Given the general purpose timers are clocked from an independent clock, this new clocksource driver will be useful to introduce CPUFreq support for Pistachio machines. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: pistachio: Allow to enable the external timer based clocksource
This commit introduces a new config, so the user can choose to enable the General Purpose Timer based clocksource. This option is required to have CPUFreq support. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: Govindraj Raja <Govindraj.Raja@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Cc: James Hogan <James.Hogan@imgtec.com> Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/10887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Fix CN6880 hang on XAUI init
Some CN68XX series Octeon II chips seem to hang if a reset is issued on XAUI initialization. Avoid the hang by disabling the reset on affected models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: http://patchwork.linux-mips.org/patch/10970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Support additional interfaces on CN68XX
CN68XX has 9 interfaces. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Support all PIP input ports on CN68XX
CN68XX has 48 PIP input ports. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Configure XAUI pkinds
Configure the pkinds of XAUI interfaces on Octeon models that have them. This simple configuration uses 1:1 mapping between the PIP input port number and the selected pkind. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Configure minimum PKO packet sizes on CN68XX
CN68XX has common minimum packet size filters that need to be configured for the traffic to work. Just set them to a default value. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10963/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Add definitions for setting up SSO
Some Octeon II models have SSO instead of POW and use a different register for setting the interrupt thresholds. Add the necessary definitions for configuring the interrupts also on those models. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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STAGING: Octeon: Properly enable/disable SSO WQE interrupts
The Octeon models with SSO instead of POW need to use a different register for configuring the WQE interrupt thresholds. Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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STAGING: Octeon: Set SSO group mask properly on CN68XX
CN68XX uses SSO instead of POW. Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10966/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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STAGING: Octeon: Increase output command buffers
The Octeon II models have more interfaces and thus require more output command buffers. Increase the allocation to support these models. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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STAGING: Octeon: Support CN68XX style WQE
CN68XX has a bit different WQE structure. This patch provides the new definitions and converts the code to use the proper variant based on the actual model. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10973/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Initialize CN68XX PKO
CN68XX requires a different PKO configuration. This patch provides just enough setup to get the XAUI interfaces on CN6880 working with default parameters. Signed-off-by: Janne Huttunen <janne.huttunen@nsn.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10974/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and ports
Use the internal port number also as the queue number on CN68XX. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Support interfaces 4 and 5
Add the support for mapping between interface/port numbers and IPD port numbers also for the additional interfaces some Octeon II models have. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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STAGING: Octeon: Use common helpers for determining interface and port
Currently the Octeon Ethernet driver hardcodes the mapping between interface/port and IPD port number. Since we have generic helpers for the very same purpose, we might as well use them instead. This prevents having the same information in multiple places. Signed-off-by: Janne Huttunen <janne.huttunen@nokia.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: Janne Huttunen <janne.huttunen@nokia.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: devel@driverdev.osuosl.org Patchwork: https://patchwork.linux-mips.org/patch/10975/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: BCM47xx: Use kmemdup rather than duplicating its implementation
The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10898/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Octeon: Fix management port MII address on Kontron S1901
Management port MII address is incorrect on Kontron S1901 resulting in broken networking. Fix by providing definitions for the in-tree DT pruning code. Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10914/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: inst.h: Add new MIPS R6 FPU opcodes
Add opcodes for the new MIPS R6 FPU instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10952/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction
Add support for emulating the new CMP.condn.fmt R6 instructions and return SIGILL for the old C.cond.fmt if R2 emulation is not enabled since it's not supported by R6. The functionality of the new CMP.condn.fmt is the following one: If the comparison specified by the condn field of the instruction is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into FPR fd; true is all 1s and false is all 0s repeated the operand width of fmt. All other bits beyond the operand width fmt are UNPREDICTABLE. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction
MIPS R6 introduced the following instruction: SELEQZ.fmt: FPR[fd] FPR[ft].bit0 ? 0 : FPR[fs] Add support for emulating the single and double precision formats of the said instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction
MIPS R6 introduced the following instruction: SELNEZ.fmt: FPR[fd] FPR[ft].bit0 ? FPR[fs] : 0 Add support for emulating the single and double precision formats of the said instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Add: MADDF.fmt To perform a fused multiply-add of FP values. MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft]) Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Subtract: MSUBF.fmt To perform a fused multiply-subtract of FP values. MSUBF.fmt: FPR[fd] = FPR[fd] - (FPR[fs] x FPR[ft]) Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10957/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction
MIPS R6 introduced the following instruction: Floating-Point Round to Integral Scalar floating-point round to integral floating point value. RINT.fmt: FPR[fd] = round_int(FPR[fs]) Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction
MIPS R6 introduced the following instruction: Stores in fd a bit mask reflecting the floating-point class of the floating point scalar value fs. CLASS.fmt: FPR[fd] = class(FPR[fs]) Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction
MIPS R6 introduced the following instruction: Scalar Floating-Point Minimum and Scalar Floating-Point argument with Minimum Absolute Value MIN.fmt writes the minimum value of the inputs fs and ft to the destination fd. MINA.fmt takes input arguments fs and ft and writes the argument with the minimum absolute value to the destination fd. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction
MIPS R6 introduced the following instruction: Scalar Floating-Point Maximum and Scalar Floating-Point argument with Maximum Absolute Value MAX.fmt writes the maximum value of the inputs fs and ft to the destination fd. MAXA.fmt takes input arguments fs and ft and writes the argument with the maximum absolute value to the destination fd. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10961/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: math-emu: Remove unused handle_dsemul function declaration
handle_dsemul does not exist and it's not being used in the code at all so remove its declaration. The deliberate DS emulation exception is handled by the do_dsemulret C code. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: Fix alignment of quiet build output for vmlinuz link
The "LD vmlinuz" line in the quiet build output is misaligned with the rest of the output. Fix this. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11019/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16.
The nomips16 has to be added both as function attribute and assembler directive. When only function attribute is specified, the compiler will inline the function with -Os optimization. The generated assembly code cannot be correctly assembled because ISA mode switch has to be done through jump instruction. When only ".set nomips16" directive is used, the generated assembly code will use MIPS32 code for the inline assembly template and MIPS16 for the function return. The compiled binary is invalid: 00403100 <__arch_swab16>: 403100: 7c0410a0 wsbh v0,a0 403104: e820ea31 swc2 $0,-5583(at) while correct code should be: 00402650 <__arch_swab16>: 402650: 7c0410a0 wsbh v0,a0 402654: 03e00008 jr ra 402658: 3042ffff andi v0,v0,0xffff Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com> Cc: Chen Jie <chenj@lemote.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11087/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Merge branches 'cleanup', 'fixes', 'misc', 'omap-barrier' and 'uacces…
…s' into for-linus
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Merge branch 'devel-stable' into for-linus
Conflicts: drivers/perf/arm_pmu.c
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pcmcia: pxa2xx: update socket driver to use devm_clk_get() API
Update the pxa2xx socket driver to use the devm_clk_get() API so that the cleanup paths are simplified. Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pcmcia: pxa2xx: convert memory allocation to devm_* API
Convert the pxa2xx socket driver memory allocation to use devm_kzalloc() to simplify the cleanup path. Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pcmcia: sa1111: update socket driver to use devm_clk_get() API
Update the pxa2xx socket driver to use the devm_clk_get() API so that the cleanup paths are simplified. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pcmcia: sa1111: simplify clk handing in sa1111_pcmcia_add()
clk_get(dev, NULL) will always refer to the same clock, so it's pointless calling this multiple times for the same device. As we no longer have to worry about the cleanup (via use of devm_clk_get()) we can simplify sa1111_pcmcia_add() too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pcmcia: sa11xx_base.c: remove useless init/exit functions
A library module is not required to have module init/exit functions. Get rid of these unnecessary functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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pcmcia: soc_common: remove skt_dev_info's clk pointer
We no longer need to store the clk pointer in struct skt_dev_info as we no longer need to remember the clk pointer for the cleanup paths. Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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When the OS/2 driver hits a disk write error, it writes the sector to another location and adds the sector mapping to the hotfix map. This patch makes the hpfs driver understand the hotfix map and remap accesses accoring to it. Signed-off-by: Mikulas Patocka <mikulas@twibright.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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hpfs: update ctime and mtime on directory modification
Update ctime and mtime when a directory is modified. (though OS/2 doesn't update them anyway) Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: stable@kernel.org # v3.3+ Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Merge branch 'hpfs' (patches from Mikulas)
Merge hpfs upddate from Mikulas Patocka. * emailed patches from Mikulas Patocka <mikulas@twibright.com>: hpfs: update ctime and mtime on directory modification hpfs: support hotfixes
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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/jack/linux-fs Pull ext3 removal, quota & udf fixes from Jan Kara: "The biggest change in the pull is the removal of ext3 filesystem driver (~28k lines removed). Ext4 driver is a full featured replacement these days and both RH and SUSE use it for several years without issues. Also there are some workarounds in VM & block layer mainly for ext3 which we could eventually get rid of. Other larger change is addition of proper error handling for dquot_initialize(). The rest is small fixes and cleanups" [ I wasn't convinced about the ext3 removal and worried about things falling through the cracks for legacy users, but ext4 maintainers piped up and were all unanimously in favor of removal, and maintaining all legacy ext3 support inside ext4. - Linus ] * 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs: udf: Don't modify filesystem for read-only mounts quota: remove an unneeded condition ext4: memory leak on error in ext4_symlink() mm/Kconfig: NEED_BOUNCE_POOL: clean-up condition ext4: Improve ext4 Kconfig test block: Remove forced page bouncing under IO fs: Remove ext3 filesystem driver doc: Update doc about journalling layer jfs: Handle error from dquot_initialize() reiserfs: Handle error from dquot_initialize() ocfs2: Handle error from dquot_initialize() ext4: Handle error from dquot_initialize() ext2: Handle error from dquot_initalize() quota: Propagate error from ->acquire_dquot()
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Merge tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/tytso/ext4 Pull ext4 updates from Ted Ts'o: "Pretty much all bug fixes and clean ups for 4.3, after a lot of features and other churn going into 4.2" * tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4: Revert "ext4: remove block_device_ejected" ext4: ratelimit the file system mounted message ext4: silence a format string false positive ext4: simplify some code in read_mmp_block() ext4: don't manipulate recovery flag when freezing no-journal fs jbd2: limit number of reserved credits ext4 crypto: remove duplicate header file ext4: update c/mtime on truncate up jbd2: avoid infinite loop when destroying aborted journal ext4, jbd2: add REQ_FUA flag when recording an error in the superblock ext4 crypto: fix spelling typo in comment ext4 crypto: exit cleanly if ext4_derive_key_aes() fails ext4: reject journal options for ext2 mounts ext4: implement cgroup writeback support ext4: replace ext4_io_submit->io_op with ->io_wbc ext4 crypto: check for too-short encrypted file names ext4 crypto: use a jbd2 transaction when adding a crypto policy jbd2: speedup jbd2_journal_dirty_metadata()
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Merge tag 'dlm-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/…
…teigland/linux-dlm Pull dlm updates from David Teigland: "This set mainly includes a change to the way the dlm uses the SCTP API in the kernel, removing the direct dependency on the sctp module. Other odd SCTP-related fixes are also included. The other notable fix is for a long standing regression in the behavior of lock value blocks for user space locks" * tag 'dlm-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm: dlm: print error from kernel_sendpage dlm: fix lvb copy for user locks dlm: sctp_accept_from_sock() can be static dlm: fix reconnecting but not sending data dlm: replace BUG_ON with a less severe handling dlm: use sctp 1-to-1 API dlm: fix not reconnecting on connecting error handling dlm: fix race while closing connections dlm: fix connection stealing if using SCTP
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Merge tag 'for-f2fs-4.3' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/jaegeuk/f2fs Pull f2fs updates from Jaegeuk Kim: "The major work includes fixing and enhancing the existing extent_cache feature, which has been well settling down so far and now it becomes a default mount option accordingly. Also, this version newly registers a f2fs memory shrinker to reclaim several objects consumed by a couple of data structures in order to avoid memory pressures. Another new feature is to add ioctl(F2FS_GARBAGE_COLLECT) which triggers a cleaning job explicitly by users. Most of the other patches are to fix bugs occurred in the corner cases across the whole code area" * tag 'for-f2fs-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs: (85 commits) f2fs: upset segment_info repair f2fs: avoid accessing NULL pointer in f2fs_drop_largest_extent f2fs: update extent tree in batches f2fs: fix to release inode correctly f2fs: handle f2fs_truncate error correctly f2fs: avoid unneeded initializing when converting inline dentry f2fs: atomically set inode->i_flags f2fs: fix wrong pointer access during try_to_free_nids f2fs: use __GFP_NOFAIL to avoid infinite loop f2fs: lookup neighbor extent nodes for merging later f2fs: split __insert_extent_tree_ret for readability f2fs: kill dead code in __insert_extent_tree f2fs: adjust showing of extent cache stat f2fs: add largest/cached stat in extent cache f2fs: fix incorrect mapping for bmap f2fs: add annotation for space utilization of regular/inline dentry f2fs: fix to update cached_en of extent tree properly f2fs: fix typo f2fs: check the node block address of newly allocated nid f2fs: go out for insert_inode_locked failure ...
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Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm…
…/linux/kernel/git/tip/tip Pull locking and atomic updates from Ingo Molnar: "Main changes in this cycle are: - Extend atomic primitives with coherent logic op primitives (atomic_{or,and,xor}()) and deprecate the old partial APIs (atomic_{set,clear}_mask()) The old ops were incoherent with incompatible signatures across architectures and with incomplete support. Now every architecture supports the primitives consistently (by Peter Zijlstra) - Generic support for 'relaxed atomics': - _acquire/release/relaxed() flavours of xchg(), cmpxchg() and {add,sub}_return() - atomic_read_acquire() - atomic_set_release() This came out of porting qwrlock code to arm64 (by Will Deacon) - Clean up the fragile static_key APIs that were causing repeat bugs, by introducing a new one: DEFINE_STATIC_KEY_TRUE(name); DEFINE_STATIC_KEY_FALSE(name); which define a key of different types with an initial true/false value. Then allow: static_branch_likely() static_branch_unlikely() to take a key of either type and emit the right instruction for the case. To be able to know the 'type' of the static key we encode it in the jump entry (by Peter Zijlstra) - Static key self-tests (by Jason Baron) - qrwlock optimizations (by Waiman Long) - small futex enhancements (by Davidlohr Bueso) - ... and misc other changes" * 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (63 commits) jump_label/x86: Work around asm build bug on older/backported GCCs locking, ARM, atomics: Define our SMP atomics in terms of _relaxed() operations locking, include/llist: Use linux/atomic.h instead of asm/cmpxchg.h locking/qrwlock: Make use of _{acquire|release|relaxed}() atomics locking/qrwlock: Implement queue_write_unlock() using smp_store_release() locking/lockref: Remove homebrew cmpxchg64_relaxed() macro definition locking, asm-generic: Add _{relaxed|acquire|release}() variants for 'atomic_long_t' locking, asm-generic: Rework atomic-long.h to avoid bulk code duplication locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations locking, compiler.h: Cast away attributes in the WRITE_ONCE() magic locking/static_keys: Make verify_keys() static jump label, locking/static_keys: Update docs locking/static_keys: Provide a selftest jump_label: Provide a self-test s390/uaccess, locking/static_keys: employ static_branch_likely() x86, tsc, locking/static_keys: Employ static_branch_likely() locking/static_keys: Add selftest locking/static_keys: Add a new static_key interface locking/static_keys: Rework update logic locking/static_keys: Add static_key_{en,dis}able() helpers ...
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/…
…linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Tooling fixes plus a handful of late arriving tooling changes" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf tools: Fix link time error with sample_reg_masks on non x86 perf build: Fix Intel PT instruction decoder dependency problem perf dwarf: Fix potential array out of bounds access perf record: Add ability to name registers to record perf/x86: Add list of register names perf script: Enable printing of interrupted machine state perf evlist: Open event on evsel cpus and threads bpf tools: New API to get name from a BPF object perf tools: Fix build on powerpc broken by pt/bts
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Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM development updates from Russell King: "Included in this update: - moving PSCI code from ARM64/ARM to drivers/ - removal of some architecture internals from global kernel view - addition of software based "privileged no access" support using the old domains register to turn off the ability for kernel loads/stores to access userspace. Only the proper accessors will be usable. - addition of early fixup support for early console - re-addition (and reimplementation) of OMAP special interconnect barrier - removal of finish_arch_switch() - only expose cpuX/online in sysfs if hotpluggable - a number of code cleanups" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (41 commits) ARM: software-based priviledged-no-access support ARM: entry: provide uaccess assembly macro hooks ARM: entry: get rid of multiple macro definitions ARM: 8421/1: smp: Collapse arch_cpu_idle_dead() into cpu_die() ARM: uaccess: provide uaccess_save_and_enable() and uaccess_restore() ARM: mm: improve do_ldrd_abort macro ARM: entry: ensure that IRQs are enabled when calling syscall_trace_exit() ARM: entry: efficiency cleanups ARM: entry: get rid of asm_trace_hardirqs_on_cond ARM: uaccess: simplify user access assembly ARM: domains: remove DOMAIN_TABLE ARM: domains: keep vectors in separate domain ARM: domains: get rid of manager mode for user domain ARM: domains: move initial domain setting value to asm/domains.h ARM: domains: provide domain_mask() ARM: domains: switch to keeping domain value in register ARM: 8419/1: dma-mapping: harmonize definition of DMA_ERROR_CODE ARM: 8417/1: refactor bitops functions with BIT_MASK() and BIT_WORD() ARM: 8416/1: Feroceon: use of_iomap() to map register base ARM: 8415/1: early fixmap support for earlycon ...
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Merge branch 'pcmcia' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM pcmcia updates from Russell King: "A series of changes updating the PXA and SA11x0 PCMCIA code to use devm_* APIs, and resolve some resource leaks in doing so. This results in a few small cleanups which are included in this set. FYI, the recommit of these today is to add Robert Jarzmik's reviewed-by tags, which I'd forgotten to add from mid-July" * 'pcmcia' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: pcmcia: soc_common: remove skt_dev_info's clk pointer pcmcia: sa11xx_base.c: remove useless init/exit functions pcmcia: sa1111: simplify clk handing in sa1111_pcmcia_add() pcmcia: sa1111: update socket driver to use devm_clk_get() API pcmcia: pxa2xx: convert memory allocation to devm_* API pcmcia: pxa2xx: update socket driver to use devm_clk_get() API pcmcia: sa11x0: convert memory allocation to devm_* API pcmcia: sa11x0: fix missing clk_put() in sa11x0 socket drivers
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Merge tag 'powerpc-4.3-1' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/powerpc/linux Pull powerpc updates from Michael Ellerman: - support "hybrid" iommu/direct DMA ops for coherent_mask < dma_mask from Benjamin Herrenschmidt - EEH fixes for SRIOV from Gavin - introduce rtas_get_sensor_fast() for IRQ handlers from Thomas Huth - use hardware RNG for arch_get_random_seed_* not arch_get_random_* from Paul Mackerras - seccomp filter support from Michael Ellerman - opal_cec_reboot2() handling for HMIs & machine checks from Mahesh Salgaonkar - add powerpc timebase as a trace clock source from Naveen N. Rao - misc cleanups in the xmon, signal & SLB code from Anshuman Khandual - add an inline function to update POWER8 HID0 from Gautham R. Shenoy - fix pte_pagesize_index() crash on 4K w/64K hash from Michael Ellerman - drop support for 64K local store on 4K kernels from Michael Ellerman - move dma_get_required_mask() from pnv_phb to pci_controller_ops from Andrew Donnellan - initialize distance lookup table from drconf path from Nikunj A Dadhania - enable RTC class support from Vaibhav Jain - disable automatically blocked PCI config from Gavin Shan - add LEDs driver for PowerNV platform from Vasant Hegde - fix endianness issues in the HVSI driver from Laurent Dufour - kexec endian fixes from Samuel Mendoza-Jonas - fix corrupted pdn list from Gavin Shan - fix fenced PHB caused by eeh_slot_error_detail() from Gavin Shan - Freescale updates from Scott: Highlights include 32-bit memcpy/memset optimizations, checksum optimizations, 85xx config fragments and updates, device tree updates, e6500 fixes for non-SMP, and misc cleanup and minor fixes. - a ton of cxl updates & fixes: - add explicit precision specifiers from Rasmus Villemoes - use more common format specifier from Rasmus Villemoes - destroy cxl_adapter_idr on module_exit from Johannes Thumshirn - destroy afu->contexts_idr on release of an afu from Johannes Thumshirn - compile with -Werror from Daniel Axtens - EEH support from Daniel Axtens - plug irq_bitmap getting leaked in cxl_context from Vaibhav Jain - add alternate MMIO error handling from Ian Munsie - allow release of contexts which have been OPENED but not STARTED from Andrew Donnellan - remove use of macro DEFINE_PCI_DEVICE_TABLE from Vaishali Thakkar - release irqs if memory allocation fails from Vaibhav Jain - remove racy attempt to force EEH invocation in reset from Daniel Axtens - fix + cleanup error paths in cxl_dev_context_init from Ian Munsie - fix force unmapping mmaps of contexts allocated through the kernel api from Ian Munsie - set up and enable PSL Timebase from Philippe Bergheaud * tag 'powerpc-4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (140 commits) cxl: Set up and enable PSL Timebase cxl: Fix force unmapping mmaps of contexts allocated through the kernel api cxl: Fix + cleanup error paths in cxl_dev_context_init powerpc/eeh: Fix fenced PHB caused by eeh_slot_error_detail() powerpc/pseries: Cleanup on pci_dn_reconfig_notifier() powerpc/pseries: Fix corrupted pdn list powerpc/powernv: Enable LEDS support powerpc/iommu: Set default DMA offset in dma_dev_setup cxl: Remove racy attempt to force EEH invocation in reset cxl: Release irqs if memory allocation fails cxl: Remove use of macro DEFINE_PCI_DEVICE_TABLE powerpc/powernv: Fix mis-merge of OPAL support for LEDS driver powerpc/powernv: Reset HILE before kexec_sequence() powerpc/kexec: Reset secondary cpu endianness before kexec powerpc/hvsi: Fix endianness issues in the HVSI driver leds/powernv: Add driver for PowerNV platform powerpc/powernv: Create LED platform device powerpc/powernv: Add OPAL interfaces for accessing and modifying system LED states powerpc/powernv: Fix the log message when disabling VF cxl: Allow release of contexts which have been OPENED but not STARTED ...
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upst…
…ream-linus Pull MIPS updates from Ralf Baechle: "This is the main pull request for 4.3 for MIPS. Here's the summary: Three fixes that didn't make 4.2-stable: - a -Os build might compile the kernel using the MIPS16 instruction set but the R2 optimized inline functions in <uapi/asm/swab.h> are implemented using 32-bit wide instructions which is invalid. - a build error in pgtable-bits.h for a particular kernel configuration. - accessing registers of the CM GCR might have been compiled to use 64 bit accesses but these registers are onl 32 bit wide. And also a few new bits: - move the ATH79 GPIO driver to drivers/gpio - the definition of IRQCHIP_DECLARE has moved to linux/irqchip.h, change ATH79 accordingly. - fix definition of pgprot_writecombine - add an implementation of dma_map_ops.mmap - fix alignment of quiet build output for vmlinuz link - BCM47xx: Use kmemdup rather than duplicating its implementation - Netlogic: Fix 0x0x prefixes of constants. - merge Bjorn Helgaas' series to remove most of the weak keywords from function declarations. - CP0 and CP1 registers are best considered treated as unsigned values to avoid large values from becoming negative values. - improve support for the MIPS GIC timer. - enable common clock framework for Malta and SEAD3. - a number of improvments and fixes to dump_tlb(). - document the MIPS TLB dump functionality in Magic SysRq. - Cavium Octeon CN68XX improvments. - NetLogic improvments. - irq: Use access helper irq_data_get_affinity_mask. - handle MSA unaligned accesses. - a number of R6-related math-emu fixes. - support for I6400. - improvments to MSA support. - add uprobes support. - move from deprecated __initcall to arch_initcall. - remove finish_arch_switch(). - IRQ cleanups by Thomas Gleixner. - migrate to new 'set-state' interface. - random small cleanups" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (148 commits) MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16. MIPS: Fix alignment of quiet build output for vmlinuz link MIPS: math-emu: Remove unused handle_dsemul function declaration MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction MIPS: inst.h: Add new MIPS R6 FPU opcodes MIPS: Octeon: Fix management port MII address on Kontron S1901 MIPS: BCM47xx: Use kmemdup rather than duplicating its implementation STAGING: Octeon: Use common helpers for determining interface and port MIPS: Octeon: Support interfaces 4 and 5 MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and ports MIPS: Octeon: Initialize CN68XX PKO STAGING: Octeon: Support CN68XX style WQE ...
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Commits on Sep 4, 2015
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/arm64/linux Pull arm64 updates from Will Deacon: - Support for new architectural features introduced in ARMv8.1: * Privileged Access Never (PAN) to catch user pointer dereferences in the kernel * Large System Extension (LSE) for building scalable atomics and locks (depends on locking/arch-atomic from tip, which is included here) * Hardware Dirty Bit Management (DBM) for updating clean PTEs automatically - Move our PSCI implementation out into drivers/firmware/, where it can be shared with arch/arm/. RMK has also pulled this component branch and has additional patches moving arch/arm/ over. MAINTAINERS is updated accordingly. - Better BUG implementation based on the BRK instruction for trapping - Leaf TLB invalidation for unmapping user pages - Support for PROBE_ONLY PCI configurations - Various cleanups and non-critical fixes, including: * Always flush FP/SIMD state over exec() * Restrict memblock additions based on range of linear mapping * Ensure *(LIST_POISON) generates a fatal fault * Context-tracking syscall return no longer corrupts return value when not forced on. * Alternatives patching synchronisation/stability improvements * Signed sub-word cmpxchg compare fix (tickled by HAVE_CMPXCHG_LOCAL) * Force SMP=y * Hide direct DCC access from userspace * Fix EFI stub memory allocation when DRAM starts at 0x0 * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) arm64: flush FP/SIMD state correctly after execve() arm64: makefile: fix perf_callchain.o kconfig dependency arm64: set MAX_MEMBLOCK_ADDR according to linear region size of/fdt: make memblock maximum physical address arch configurable arm64: Fix source code file path in comments arm64: entry: always restore x0 from the stack on syscall return arm64: mdscr_el1: avoid exposing DCC to userspace arm64: kconfig: Move LIST_POISON to a safe value arm64: Add __exception_irq_entry definition for function graph arm64: mm: ensure patched kernel text is fetched from PoU arm64: alternatives: ensure secondary CPUs execute ISB after patching arm64: make ll/sc __cmpxchg_case_##name asm consistent arm64: dma-mapping: Simplify pgprot handling arm64: restore cpu suspend/resume functionality ARM64: PCI: do not enable resources on PROBE_ONLY systems arm64: cmpxchg: truncate sub-word signed types before comparison arm64: alternative: put secondary CPUs into polling loop during patch arm64/Documentation: clarify wording regarding memory below the Image arm64: lse: fix lse cmpxchg code indentation arm64: remove redundant object file list ...
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile
Pull tile updates from Chris Metcalf: "This includes secure computing support as well as miscellaneous minor improvements" * git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: tile: correct some typos in opcode type names tile/vdso: emit a GNU hash as well tile: Remove finish_arch_switch tile: enable full SECCOMP support tile/time: Migrate to new 'set-state' interface
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Merge tag 'gpio-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.3 kernel cycle. There is quite a lot going on in the GPIO subsystem this merge window, so the main matter is decribed below. The hits in other subsystems when making the GPIO flags optional are all ACKed by their respective subsystem maintainers. Core changes: - Root out the wrapper devm_gpiod_get() and gpiod_get() etc versions of the descriptor calls that did not use the flags argument on the end. This was around for too long and eventually Uwe Kleine-König took the time to clean it out and the last users are removed along with the macros in this tag. In several cases the use of flags simplifies the code. For this reason we have (ACKed) patches hitting in DRM, IIO, media, NFC, USB+PHY up until we hammer in the nail with removing the macros. - Add a fat document describing how much ready-made GPIO stuff we have i the kernel to discourage people from reinventing a square wheel in userspace, as so often happens. - Create a separate lockdep class for each instance of a GPIO IRQ chip instead of using one class for all chips, as the current code will not work with systems with several GPIO chips doing lockdep debugging. - Protect against driver unloading also when a GPIO line is only used as IRQ for the GPIOLIB_IRQCHIP helpers. - If the GPIO chip has no designated owner, assign the parent device driver owner as owner. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx and Jiang Liu wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. - Rob Herring killed off the set_irq_flags() for all GPIO drivers. This was an ARM specific function that is replaced with the generic irq_modify_status() where special flags are actually needed. - When an OF node has a pin range for its GPIOs, return -EPROBE_DEFER if the pin controller isn't available. Pretty logical, yet needed to be fixed. - If a driver using GPIOLIB_IRQCHIP has its own irq_*_resources call back, then call these instead of the defaults provided by the GPIOLIB. - Fix an undocumented ABI hole: named GPIOs were not properly documented. Driver improvements: - Add get_direction() support to the generic GPIO driver, it's strange that we didn't have that before. - Make it possible to have input-only GPIO chips using the generic GPIO driver. - Clean out platform data support from the Emma Mobile (EM) driver - Finegrained runtime PM support for the RCAR driver. - Support r8a7795 (R-car H3) in the RCAR driver. - Support interrupts on GPIOs 16 thru 31 in the DaVinci driver. - Some consolidation and new support in the MPC8xxx driver, we now support MPC5125. - Preempt-RT-friendly patches: the OMAP, MPC8xxx, drivers uses raw spinlocks making it work better with the realime patches. - Interrupt support for the EXTRAXFS GPIO driver. - Make the ETRAXFS GPIO driver support also ARTPEC-3. - Interrupt and wakeup support for the BRCMSTB driver, also for wakeup from S5 cold boot. - Mask MXC IRQs during suspend. - Improve OMAP2 GPIO set_debounce() to work according to spec. - The VF610 driver handles IRQs properly. New drivers: - ZTE ZX GPIO driver" * tag 'gpio-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (87 commits) Revert "gpio: extraxfs: fix returnvar.cocci warnings" gpio: tc3589x: use static container helper gpio: xlp: fix error return code gpio: vf610: handle level IRQ's properly gpio: max732x: Fix error handling in probe() gpio: omap: fix clk_prepare/unprepare usage gpio: omap: protect regs access in omap_gpio_irq_handler gpio: omap: fix omap2_set_gpio_debounce gpio: omap: switch to use platform_get_irq gpio: omap: remove wrong irq_domain_remove usage in probe gpiolib: add description for gpio irqchip fields in struct gpio_chip gpio: extraxfs: fix returnvar.cocci warnings gpiolib: irqchip: use different lockdep class for each gpio irqchip gpio/grgpio: fix deadlock in grgpio_irq_unmap() Documentation: gpio: consumer: describe active low property gpio: mxc: fix section mismatch warning gpio/mxc: mask gpio interrupts in suspend gpio: omap: Fix missing raw locks conversion gpio: brcmstb: support wakeup from S5 cold boot gpio: brcmstb: Add interrupt and wakeup source support ...
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
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