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1. ariane ariane Public

   Forked from openhwgroup/cva6

   Ariane is a 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog

2. common_cells common_cells Public

   Forked from pulp-platform/common_cells

   Common SV components

   SystemVerilog

3. axi axi Public

   Forked from pulp-platform/axi

   AXI4 and AXI4-Lite interface definitions and testbench utilities

   SystemVerilog

4. axi_node axi_node Public

   Forked from pulp-platform/axi_node

   AXI X-Bar

   SystemVerilog

5. axi_slice axi_slice Public

   Forked from pulp-platform/axi_slice

   Pipelines the AXI path with FIFOs

   SystemVerilog

6. fpnew fpnew Public

   Forked from openhwgroup/cvfpu

   Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

   SystemVerilog 1