DAOS-14532 gurt: Replace environment APIs hook

Integrate reviewers comments:
- Revert d_getenv_XXX interfaces update
- Rename d_free_env() -> d_free_env_str()

Features: mpiio
Required-githooks: true
Signed-off-by: Cedric Koch-Hofer <cedric.koch-hofer@intel.com>

src/bio/bio_xstream.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2018-2023 Intel Corporation.
+ * (C) Copyright 2018-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -195,9 +195,9 @@ set_faulty_criteria(void)
 	 */
 	glb_criteria.fc_max_csum_errs = UINT32_MAX;
 
-	d_getenv_bool(&glb_criteria.fc_enabled, "DAOS_NVME_AUTO_FAULTY_ENABLED");
-	d_getenv_uint32_t(&glb_criteria.fc_max_io_errs, "DAOS_NVME_AUTO_FAULTY_IO");
-	d_getenv_uint32_t(&glb_criteria.fc_max_csum_errs, "DAOS_NVME_AUTO_FAULTY_CSUM");
+	d_getenv_bool("DAOS_NVME_AUTO_FAULTY_ENABLED", &glb_criteria.fc_enabled);
+	d_getenv_uint32_t("DAOS_NVME_AUTO_FAULTY_IO", &glb_criteria.fc_max_io_errs);
+	d_getenv_uint32_t("DAOS_NVME_AUTO_FAULTY_CSUM", &glb_criteria.fc_max_csum_errs);
 
 	D_INFO("NVMe auto faulty is %s. Criteria: max_io_errs:%u, max_csum_errs:%u\n",
 	       glb_criteria.fc_enabled ? "enabled" : "disabled",
@@ -246,18 +246,18 @@ bio_nvme_init(const char *nvme_conf, int numa_node, unsigned int mem_size,
 	bio_chk_cnt_max = DAOS_DMA_CHUNK_CNT_MAX;
 	bio_chk_sz = ((uint64_t)size_mb << 20) >> BIO_DMA_PAGE_SHIFT;
 
-	d_getenv_bool(&bio_scm_rdma, "DAOS_SCM_RDMA_ENABLED");
+	d_getenv_bool("DAOS_SCM_RDMA_ENABLED", &bio_scm_rdma);
 	D_INFO("RDMA to SCM is %s\n", bio_scm_rdma ? "enabled" : "disabled");
 
-	d_getenv_uint(&bio_spdk_subsys_timeout, "DAOS_SPDK_SUBSYS_TIMEOUT");
+	d_getenv_uint("DAOS_SPDK_SUBSYS_TIMEOUT", &bio_spdk_subsys_timeout);
 	D_INFO("SPDK subsystem fini timeout is %u ms\n", bio_spdk_subsys_timeout);
 
-	d_getenv_uint(&bio_spdk_max_unmap_cnt, "DAOS_SPDK_MAX_UNMAP_CNT");
+	d_getenv_uint("DAOS_SPDK_MAX_UNMAP_CNT", &bio_spdk_max_unmap_cnt);
 	if (bio_spdk_max_unmap_cnt == 0)
 		bio_spdk_max_unmap_cnt = UINT32_MAX;
 	D_INFO("SPDK batch blob unmap call count is %u\n", bio_spdk_max_unmap_cnt);
 
-	d_getenv_uint(&bio_max_async_sz, "DAOS_MAX_ASYNC_SZ");
+	d_getenv_uint("DAOS_MAX_ASYNC_SZ", &bio_max_async_sz);
 	D_INFO("Max async data size is set to %u bytes\n", bio_max_async_sz);
 
 	/* Hugepages disabled */

src/cart/crt_init.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -192,7 +192,7 @@ prov_data_init(struct crt_prov_gdata *prov_data, crt_provider_t provider,
 
 	/* Set max number of contexts. Defaults to the number of cores */
 	ctx_num = 0;
-	d_getenv_uint(&ctx_num, "CRT_CTX_NUM");
+	d_getenv_uint("CRT_CTX_NUM", &ctx_num);
 	if (opt)
 		max_num_ctx = ctx_num ? ctx_num : max(crt_gdata.cg_num_cores, opt->cio_ctx_max_num);
 	else
@@ -217,11 +217,11 @@ prov_data_init(struct crt_prov_gdata *prov_data, crt_provider_t provider,
 		} else {
 			share_addr = false;
 
-			d_getenv_bool(&share_addr, "CRT_CTX_SHARE_ADDR");
+			d_getenv_bool("CRT_CTX_SHARE_ADDR", &share_addr);
 			if (share_addr) {
 				set_sep = true;
 				ctx_num = 0;
-				d_getenv_uint(&ctx_num, "CRT_CTX_NUM");
+				d_getenv_uint("CRT_CTX_NUM", &ctx_num);
 				max_num_ctx = ctx_num;
 			}
 		}
@@ -279,30 +279,30 @@ static int data_init(int server, crt_init_options_t *opt)
 		crt_gdata.cg_rpcid, crt_gdata.cg_num_cores);
 
 	/* Set context post init / post incr to tune number of pre-posted recvs */
-	d_getenv_uint32_t(&post_init, "D_POST_INIT");
+	d_getenv_uint32_t("D_POST_INIT", &post_init);
 	crt_gdata.cg_post_init = post_init;
-	d_getenv_uint32_t(&post_incr, "D_POST_INCR");
+	d_getenv_uint32_t("D_POST_INCR", &post_incr);
 	crt_gdata.cg_post_incr = post_incr;
 
 	is_secondary = 0;
 	/* Apply CART-890 workaround for server side only */
 	if (server) {
-		d_getenv_uint(&mem_pin_enable, "CRT_ENABLE_MEM_PIN");
+		d_getenv_uint("CRT_ENABLE_MEM_PIN", &mem_pin_enable);
 		if (mem_pin_enable == 1)
 			mem_pin_workaround();
 	} else {
 		/*
 		 * Client-side envariable to indicate that the cluster
 		 * is running using a secondary provider
 		 */
-		d_getenv_uint(&is_secondary, "CRT_SECONDARY_PROVIDER");
+		d_getenv_uint("CRT_SECONDARY_PROVIDER", &is_secondary);
 	}
 	crt_gdata.cg_provider_is_primary = (is_secondary) ? 0 : 1;
 
 	if (opt && opt->cio_crt_timeout != 0)
 		timeout = opt->cio_crt_timeout;
 	else
-		d_getenv_uint(&timeout, "CRT_TIMEOUT");
+		d_getenv_uint("CRT_TIMEOUT", &timeout);
 
 	if (timeout == 0 || timeout > 3600)
 		crt_gdata.cg_timeout = CRT_DEFAULT_TIMEOUT_S;
@@ -321,13 +321,13 @@ static int data_init(int server, crt_init_options_t *opt)
 		credits = opt->cio_ep_credits;
 	} else {
 		credits = CRT_DEFAULT_CREDITS_PER_EP_CTX;
-		d_getenv_uint(&credits, "CRT_CREDIT_EP_CTX");
+		d_getenv_uint("CRT_CREDIT_EP_CTX", &credits);
 	}
 
 	/* Enable quotas by default only on clients */
 	crt_gdata.cg_rpc_quota = server ? 0 : CRT_QUOTA_RPCS_DEFAULT;
 
-	d_getenv_int("D_QUOTA_RPCS", &crt_gdata.cg_rpc_quota);
+	d_getenv_uint("D_QUOTA_RPCS", &crt_gdata.cg_rpc_quota);
 
 	/* Must be set on the server when using UCX, will not affect OFI */
 	d_getenv_char("UCX_IB_FORK_INIT", &ucx_ib_fork_init);
@@ -342,7 +342,7 @@ static int data_init(int server, crt_init_options_t *opt)
 		d_setenv("UCX_IB_FORK_INIT", "n", 1);
 
 	/* This is a workaround for CART-871 if universe size is not set */
-	d_getenv_uint(&fi_univ_size, "FI_UNIVERSE_SIZE");
+	d_getenv_uint("FI_UNIVERSE_SIZE", &fi_univ_size);
 	if (fi_univ_size == 0) {
 		D_INFO("FI_UNIVERSE_SIZE was not set; setting to 2048\n");
 		d_setenv("FI_UNIVERSE_SIZE", "2048", 1);
@@ -566,7 +566,7 @@ prov_settings_apply(bool primary, crt_provider_t prov, crt_init_options_t *opt)
 	if (prov == CRT_PROV_OFI_CXI)
 		mrc_enable = 1;
 
-	d_getenv_uint(&mrc_enable, "CRT_MRC_ENABLE");
+	d_getenv_uint("CRT_MRC_ENABLE", &mrc_enable);
 	if (mrc_enable == 0) {
 		D_INFO("Disabling MR CACHE (FI_MR_CACHE_MAX_COUNT=0)\n");
 		d_setenv("FI_MR_CACHE_MAX_COUNT", "0", 1);
@@ -733,7 +733,7 @@ crt_init_opt(crt_group_id_t grpid, uint32_t flags, crt_init_options_t *opt)
 				port_str = tmp;
 		}
 
-		d_getenv_bool(&port_auto_adjust, "D_PORT_AUTO_ADJUST");
+		d_getenv_bool("D_PORT_AUTO_ADJUST", &port_auto_adjust);
 
 		rc = __split_arg(provider_env, &provider_str0, &provider_str1);
 		if (rc != 0)

src/cart/swim/swim.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016 UChicago Argonne, LLC
- * (C) Copyright 2018-2023 Intel Corporation.
+ * (C) Copyright 2018-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -25,7 +25,7 @@ swim_prot_period_len_default(void)
 {
 	unsigned int val = SWIM_PROTOCOL_PERIOD_LEN;
 
-	d_getenv_uint(&val, "SWIM_PROTOCOL_PERIOD_LEN");
+	d_getenv_uint("SWIM_PROTOCOL_PERIOD_LEN", &val);
 	return val;
 }
 
@@ -34,7 +34,7 @@ swim_suspect_timeout_default(void)
 {
 	unsigned int val = SWIM_SUSPECT_TIMEOUT;
 
-	d_getenv_uint(&val, "SWIM_SUSPECT_TIMEOUT");
+	d_getenv_uint("SWIM_SUSPECT_TIMEOUT", &val);
 	return val;
 }
 
@@ -43,7 +43,7 @@ swim_ping_timeout_default(void)
 {
 	unsigned int val = SWIM_PING_TIMEOUT;
 
-	d_getenv_uint(&val, "SWIM_PING_TIMEOUT");
+	d_getenv_uint("SWIM_PING_TIMEOUT", &val);
 	return val;
 }
 

src/client/api/event.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -97,7 +97,7 @@ daos_eq_lib_init()
 
 	eq_ref = 1;
 
-	d_getenv_uint32_t(&ev_prog_timeout, "D_POLL_TIMEOUT");
+	d_getenv_uint32_t("D_POLL_TIMEOUT", &ev_prog_timeout);
 
 unlock:
 	D_MUTEX_UNLOCK(&daos_eq_lock);

src/client/dfs/dfs.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2018-2023 Intel Corporation.
+ * (C) Copyright 2018-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -2267,7 +2267,7 @@ dfs_mount(daos_handle_t poh, daos_handle_t coh, int flags, dfs_t **_dfs)
 	 * mode.
 	 */
 	if ((dfs->attr.da_mode & MODE_MASK) == DFS_RELAXED)
-		d_getenv_bool(&dfs->use_dtx, "DFS_USE_DTX");
+		d_getenv_bool("DFS_USE_DTX", &dfs->use_dtx);
 
 	/** Check if super object has the root entry */
 	strcpy(dfs->root.name, "/");

src/client/dfuse/il/int_posix.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2017-2023 Intel Corporation.
+ * (C) Copyright 2017-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -313,7 +313,7 @@ ioil_init(void)
 	/* Check what progress to report on.  If the env is set but could not be
 	 * parsed then just show the summary (report_count will be 0).
 	 */
-	rc = d_getenv_uint64_t(&report_count, "D_IL_REPORT");
+	rc = d_getenv_uint64_t("D_IL_REPORT", &report_count);
 	if (rc != -DER_NONEXIST) {
 		ioil_iog.iog_show_summary = true;
 		ioil_iog.iog_report_count = report_count;
@@ -331,7 +331,7 @@ ioil_init(void)
 	if (rc)
 		return;
 
-	rc = d_getenv_uint64_t(&eq_count, "D_IL_MAX_EQ");
+	rc = d_getenv_uint64_t("D_IL_MAX_EQ", &eq_count);
 	if (rc != -DER_NONEXIST) {
 		if (eq_count > IOIL_MAX_EQ) {
 			DFUSE_LOG_WARNING("Max EQ count (%"PRIu64") should not exceed: %d",

src/client/dfuse/pil4dfs/int_dfs.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2022-2023 Intel Corporation.
+ * (C) Copyright 2022-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -5553,7 +5553,7 @@ init_myhook(void)
 	rc = D_MUTEX_INIT(&lock_eqh, NULL);
 	if (rc)
 		return;
-	rc = d_getenv_uint64_t(&eq_count_loc, "D_IL_MAX_EQ");
+	rc = d_getenv_uint64_t("D_IL_MAX_EQ", &eq_count_loc);
 	if (rc != -DER_NONEXIST) {
 		if (eq_count_loc > MAX_EQ) {
 			D_WARN("Max EQ count (%" PRIu64 ") should not exceed: %d", eq_count_loc,

src/common/mem.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -61,7 +61,7 @@ umempobj_settings_init(bool md_on_ssd)
 		return rc;
 	}
 
-	d_getenv_uint(&md_mode, "DAOS_MD_ON_SSD_MODE");
+	d_getenv_uint("DAOS_MD_ON_SSD_MODE", &md_mode);
 
 	switch (md_mode) {
 	case DAOS_MD_BMEM:

src/common/misc.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -656,7 +656,7 @@ daos_crt_init_opt_get(bool server, int ctx_nr)
 	daos_crt_init_opt.cio_use_sensors = server;
 
 	/** configure cart for maximum bulk threshold */
-	d_getenv_uint32_t(&limit, "DAOS_RPC_SIZE_LIMIT");
+	d_getenv_uint32_t("DAOS_RPC_SIZE_LIMIT", &limit);
 
 	daos_crt_init_opt.cio_use_expected_size = 1;
 	daos_crt_init_opt.cio_max_expected_size = limit ? limit : DAOS_RPC_SIZE;
@@ -674,7 +674,7 @@ daos_crt_init_opt_get(bool server, int ctx_nr)
 	}
 
 	/** Scalable EndPoint-related settings */
-	d_getenv_bool(&sep, "CRT_CTX_SHARE_ADDR");
+	d_getenv_bool("CRT_CTX_SHARE_ADDR", &sep);
 	if (!sep)
 		goto out;
 

src/dtx/dtx_srv.c

@@ -1,5 +1,5 @@
 /**
- * (C) Copyright 2019-2023 Intel Corporation.
+ * (C) Copyright 2019-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -512,7 +512,7 @@ dtx_init(void)
 	int	rc;
 
 	dtx_agg_thd_cnt_up = DTX_AGG_THD_CNT_DEF;
-	d_getenv_uint32_t(&dtx_agg_thd_cnt_up, "DAOS_DTX_AGG_THD_CNT");
+	d_getenv_uint32_t("DAOS_DTX_AGG_THD_CNT", &dtx_agg_thd_cnt_up);
 	if (dtx_agg_thd_cnt_up < DTX_AGG_THD_CNT_MIN || dtx_agg_thd_cnt_up > DTX_AGG_THD_CNT_MAX) {
 		D_WARN("Invalid DTX aggregation count threshold %u, the valid range is [%u, %u], "
 		       "use the default value %u\n", dtx_agg_thd_cnt_up, DTX_AGG_THD_CNT_MIN,
@@ -524,7 +524,7 @@ dtx_init(void)
 	D_INFO("Set DTX aggregation count threshold as %u (entries)\n", dtx_agg_thd_cnt_up);
 
 	dtx_agg_thd_age_up = DTX_AGG_THD_AGE_DEF;
-	d_getenv_uint32_t(&dtx_agg_thd_age_up, "DAOS_DTX_AGG_THD_AGE");
+	d_getenv_uint32_t("DAOS_DTX_AGG_THD_AGE", &dtx_agg_thd_age_up);
 	if (dtx_agg_thd_age_up < DTX_AGG_THD_AGE_MIN || dtx_agg_thd_age_up > DTX_AGG_THD_AGE_MAX) {
 		D_WARN("Invalid DTX aggregation age threshold %u, the valid range is [%u, %u], "
 		       "use the default value %u\n", dtx_agg_thd_age_up, DTX_AGG_THD_AGE_MIN,
@@ -536,7 +536,7 @@ dtx_init(void)
 	D_INFO("Set DTX aggregation time threshold as %u (seconds)\n", dtx_agg_thd_age_up);
 
 	dtx_batched_ult_max = DTX_BATCHED_ULT_DEF;
-	d_getenv_uint32_t(&dtx_batched_ult_max, "DAOS_DTX_BATCHED_ULT_MAX");
+	d_getenv_uint32_t("DAOS_DTX_BATCHED_ULT_MAX", &dtx_batched_ult_max);
 	D_INFO("Set the max count of DTX batched commit ULTs as %d\n", dtx_batched_ult_max);
 
 	rc = dbtree_class_register(DBTREE_CLASS_DTX_CF,

src/engine/init.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -314,7 +314,7 @@ dss_topo_init()
 	dss_core_nr = hwloc_get_nbobjs_by_type(dss_topo, HWLOC_OBJ_CORE);
 	depth = hwloc_get_type_depth(dss_topo, HWLOC_OBJ_NUMANODE);
 	numa_node_nr = hwloc_get_nbobjs_by_depth(dss_topo, depth);
-	d_getenv_bool(&tgt_oversub, "DAOS_TARGET_OVERSUBSCRIBE");
+	d_getenv_bool("DAOS_TARGET_OVERSUBSCRIBE", &tgt_oversub);
 	dss_tgt_nr = nr_threads;
 
 	/* if no NUMA node was specified, or NUMA data unavailable */

src/engine/srv.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2016-2023 Intel Corporation.
+ * (C) Copyright 2016-2024 Intel Corporation.
  *
  * SPDX-License-Identifier: BSD-2-Clause-Patent
  */
@@ -393,7 +393,7 @@ dss_srv_handler(void *arg)
 	if (rc)
 		goto signal;
 
-	d_getenv_bool(&track_mem, D_MEMORY_TRACK_ENV);
+	d_getenv_bool(D_MEMORY_TRACK_ENV, &track_mem);
 	if (unlikely(track_mem))
 		d_set_alloc_track_cb(dss_mem_total_alloc_track, dss_mem_total_free_track,
 				     &dx->dx_mem_stats);
@@ -1027,17 +1027,17 @@ dss_xstreams_init(void)
 
 	D_ASSERT(dss_tgt_nr >= 1);
 
-	d_getenv_bool(&sched_prio_disabled, "DAOS_SCHED_PRIO_DISABLED");
+	d_getenv_bool("DAOS_SCHED_PRIO_DISABLED", &sched_prio_disabled);
 	if (sched_prio_disabled)
 		D_INFO("ULT prioritizing is disabled.\n");
 
 #ifdef ULT_MMAP_STACK
-	d_getenv_bool(&daos_ult_mmap_stack, "DAOS_ULT_MMAP_STACK");
+	d_getenv_bool("DAOS_ULT_MMAP_STACK", &daos_ult_mmap_stack);
 	if (daos_ult_mmap_stack == false)
 		D_INFO("ULT mmap()'ed stack allocation is disabled.\n");
 #endif
 
-	d_getenv_uint(&sched_relax_intvl, "DAOS_SCHED_RELAX_INTVL");
+	d_getenv_uint("DAOS_SCHED_RELAX_INTVL", &sched_relax_intvl);
 	if (sched_relax_intvl == 0 ||
 	    sched_relax_intvl > SCHED_RELAX_INTVL_MAX) {
 		D_WARN("Invalid relax interval %u, set to default %u msecs.\n",
@@ -1059,8 +1059,8 @@ dss_xstreams_init(void)
 	D_INFO("CPU relax mode is set to [%s]\n",
 	       sched_relax_mode2str(sched_relax_mode));
 
-	d_getenv_uint(&sched_unit_runtime_max, "DAOS_SCHED_UNIT_RUNTIME_MAX");
-	d_getenv_bool(&sched_watchdog_all, "DAOS_SCHED_WATCHDOG_ALL");
+	d_getenv_uint("DAOS_SCHED_UNIT_RUNTIME_MAX", &sched_unit_runtime_max);
+	d_getenv_bool("DAOS_SCHED_WATCHDOG_ALL", &sched_watchdog_all);
 
 	/* start the execution streams */
 	D_DEBUG(DB_TRACE,