Boards openroad added

.bazelversion

@@ -0,0 +1 @@
+7.4.0

.gitignore

@@ -14,3 +14,7 @@ build
 iseconfig
 *.a
 *.bin
+bazel-bin
+bazel-darkriscv
+bazel-out
+bazel-testlogs

BUILD.bazel

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+"""Top level Bazel module, allows access to files by other modules."""
+
+exports_files(
+    glob([
+        "rtl/**/*.v",
+        "rtl/**/*.vh",
+    ]),
+    visibility = [":__subpackages__"],
+)
+
+filegroup(
+    name = "verilog",
+    srcs = glob(
+        ["rtl/**/*.v"],
+        # FIXME delete this on next upgrade of ORFS
+        exclude = ["rtl/darksocv.v"],
+    ) + [
+        ":darksocv_cleaned",
+    ],
+    visibility = [":__subpackages__"],
+)
+
+# FIXME delete this on next upgrade of ORFS, it handles $display() statements
+genrule(
+    name = "darksocv_cleaned",
+    srcs = [
+        ":rtl/darksocv.v",
+        ":rtl/config.vh",
+    ],
+    outs = [
+        ":cleaned/rtl/darksocv_cleaned.v",
+        ":cleaned/rtl/config.vh",
+    ],
+    cmd = """
+    sed -e "/\\$$display/d" $(location :rtl/darksocv.v) > $(location :cleaned/rtl/darksocv_cleaned.v)
+    cp $(location :rtl/config.vh) $(location :cleaned/rtl/config.vh)
+    """,
+)
+
+filegroup(
+    name = "verilog_include",
+    srcs = glob(["rtl/**/*.vh"]),
+    visibility = [":__subpackages__"],
+)
+
+filegroup(
+    name = "verilog_data",
+    srcs = glob(["src/**/*.mem"]),
+    visibility = [":__subpackages__"],
+)

MODULE.bazel

@@ -0,0 +1,23 @@
+"""Bazel depedencies"""
+
+module(
+    name = "darkriscv",
+    version = "0.0.1",
+    compatibility_level = 1,
+)
+
+bazel_dep(name = "bazel-orfs")
+git_override(
+    module_name = "bazel-orfs",
+    commit = "b16da67e50032682dc6f01252217bfb71cf89260",
+    remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
+)
+
+orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories")
+orfs.default(
+    # To update, find latest at https://hub.docker.com/r/openroad/orfs/tags
+    image = "docker.io/openroad/orfs:v3.0-2591-g9bca87d7",
+    sha256 = "673181c3b49235cf5b43e386e4cf478d676b797c8b7736a3ed79fc90f4c8acb7",
+)
+use_repo(orfs, "com_github_nixos_patchelf_download")
+use_repo(orfs, "docker_orfs")

boards/openroad/BUILD.bazel

@@ -0,0 +1,68 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_flow")
+
+FASTER = {
+    # ignore timing repair for now
+    "SETUP_SLACK_MARGIN": "-1000",
+    "SKIP_REPORT_METRICS": "1",
+    "SKIP_LAST_GASP": "1",
+    # skip checks for now, faster
+    "PWR_NETS_VOLTAGES": "",
+    "GND_NETS_VOLTAGES": "",
+}
+
+# SRAMs are specific to PDK, mock one here by
+# creating it from flip flops and use mock_area
+# to reduce the size of the SRAM to something that
+# is a bit more reasonable.
+orfs_flow(
+    name = "darkram",
+    abstract_stage = "cts",
+    arguments = FASTER | {
+        "CORE_UTILIZATION": "10",
+        "SYNTH_MEMORY_MAX_BITS": "65536",
+        "MACRO_BLOCKAGE_HALO": "0",
+        "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl",
+    },
+    # The width/height of a real SRAM might be, say,
+    # 25% of that of a flip flop based SRAM.
+    mock_area = 0.25,
+    sources = {
+        "SDC_FILE": [":constraints_darkram.sdc"],
+    },
+    stage_data = {
+        "synth": [
+            "//:verilog_data",
+            "//:verilog_include",
+        ],
+    },
+    # OpenROAD version of the darkram.v file
+    verilog_files = [":darkram.v"],
+)
+
+orfs_flow(
+    name = "darksocv",
+    arguments = FASTER | {
+        "SYNTH_HIERARCHICAL": "1",
+        #"SYNTH_MINIMUM_KEEP_SIZE": "1",
+        "CORE_UTILIZATION": "40",
+        "MIN_ROUTING_LAYER": "M2",
+        "MAX_ROUTING_LAYER": "M7",
+        "CORE_MARGIN": "2",
+        "MACRO_PLACE_HALO": "2 2",
+        "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
+        "GDS_ALLOW_EMPTY": "darkram",
+    },
+    macros = ["darkram_generate_abstract"],
+    sources = {
+        "SDC_FILE": [":constraints.sdc"],
+    },
+    stage_data = {
+        "synth": [
+            "//:verilog_data",
+            "//:verilog_include",
+        ],
+    },
+    verilog_files = [
+        "//:verilog",
+    ],
+)

boards/openroad/README.md

@@ -0,0 +1,32 @@
+OpenROAD ASAP7 PDK configuration
+================================
+
+TL;DR Install Bazelisk and run command below to build and view darksocv in the GUI, Bazelisk handles all depedencies.
+
+Demonstrates how to set up an [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) to build darksocv with [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts)
+
+To build and view [Install Bazelisk](https://bazel.build/install/bazelisk) and run:
+
+    bazelisk run //boards/openroad:darksocv_cts /tmp/cts gui_cts
+
+Register to register histogram
+------------------------------
+
+![alt text](reg2reg-histogram.png)
+
+Estimated routing congestion
+----------------------------
+
+![alt text](routing-congestion.png)
+
+Ideas for future work
+=====================
+
+- reduce clock period
+- darkram.v should consist of serveral SRAMs connected together to be
+  a more accurate representation
+- create a mock SRAM representation with somewhat realistic timing
+- add IO constraints to place pins on one edge of the SRAMs and top level
+- reduce area
+
+[MegaBoom](https://github.com/The-OpenROAD-Project/megaboom) demonstrates a number of techniques to study a design and set up mock SRAMs.

boards/openroad/constraints.sdc

@@ -0,0 +1,5 @@
+set clk_name XCLK
+set clk_port_name XCLK
+set clk_period 2000
+
+source $::env(PLATFORM_DIR)/constraints.sdc

boards/openroad/constraints_darkram.sdc

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+set sdc_version 2.0
+
+set clk_name CLK
+set clk_port_name CLK
+set clk_period 2000
+
+set clk_port [get_ports $clk_port_name]
+create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
+
+set non_clk_inputs  [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
+set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers]
+set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs]
+set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs]
+# group_path -name in2reg -from $non_clk_inputs -to [all_registers]
+# group_path -name reg2out -from [all_registers] -to [all_outputs]
+# group_path -name in2out -from $non_clk_inputs -to [all_outputs]