Phytium: Merge some basic information of Phytium SOCs.

Documentation/devicetree/bindings/vendor-prefixes.yaml

@@ -1045,6 +1045,8 @@ patternProperties:
     description: PHICOMM Co., Ltd.
   "^phytec,.*":
     description: PHYTEC Messtechnik GmbH
+  "^phytium,.*":
+    description: Phytium Technology Co., Ltd.
   "^picochip,.*":
     description: Picochip Ltd
   "^pine64,.*":

MAINTAINERS

@@ -17420,6 +17420,12 @@ F:	include/sound/pxa2xx-lib.h
 F:	sound/arm/pxa*
 F:	sound/soc/pxa/
 
+ARM/PHYTIUM SOC SUPPORT
+M:	Wang Yinfeng <wangyinfeng@phytium.com.cn>
+S:	Maintained
+W:	https://gerrit.b.cpu.ac/c/linux
+F:	arch/arm64/boot/dts/phytium/*
+
 QAT DRIVER
 M:	Giovanni Cabiddu <giovanni.cabiddu@intel.com>
 L:	qat-linux@intel.com

arch/arm64/Kconfig.platforms

@@ -244,6 +244,14 @@ config ARCH_NPCM
 	  General support for NPCM8xx BMC (Arbel).
 	  Nuvoton NPCM8xx BMC based on the Cortex A35.
 
+config ARCH_PHYTIUM
+	bool "Phytium SoC Family"
+	help
+	  This enables support for Phytium ARMv8 SoC family, including:
+	   - Phytium Server SoC Family
+	   - Phytium Desktop SoC Family
+	   - Phytium Embedded SoC Family
+
 config ARCH_QCOM
 	bool "Qualcomm Platforms"
 	select GPIOLIB

arch/arm64/boot/dts/phytium/Makefile

@@ -0,0 +1,9 @@
+dtb-$(CONFIG_ARCH_PHYTIUM) += pe2204-demo-ddr4.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += pe2204-demo-ddr4-local.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += pe2202-demo-ddr4.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += pe2202-demo-ddr4-local.dtb
+dtb-$(CONFIG_ARCH_PHYTIUM) += pe2201-demo-ddr4.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb

arch/arm64/boot/dts/phytium/pe2201-demo-ddr4.dts

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS file for Phytium Pe2201 demo board
+ *
+ * Copyright (C) 2022-2023, Phytium Technology Co., Ltd.
+ */
+
+/dts-v1/;
+/memreserve/ 0x80000000 0x10000;
+
+#include "pe2201.dtsi"
+
+/{
+	model = "Pe2201 DEMO DDR4";
+	compatible = "phytium,pe2201";
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&soc {
+	mio9: i2c@28026000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28026000 0x0 0x1000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&usb2_0 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_2 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&macb0 {
+	phy-mode = "sgmii";
+	use-mii;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&mmc0 {
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+};

arch/arm64/boot/dts/phytium/pe2201.dtsi

@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Phytium Pe2201 SoC
+ *
+ * Copyright (C) 2022-2023, Phytium Technology Co., Ltd.
+ */
+
+#include "pe220x.dtsi"
+
+/ {
+	compatible = "phytium,pe2201";
+
+	aliases {
+		ethernet0 = &macb0;
+		ethernet1 = &macb1;
+	};
+};
+
+&cpu {
+	cpu0: cpu@0 {
+		device_type = "cpu";
+		compatible = "phytium,ftc310", "arm,armv8";
+		reg = <0x0 0x200>;
+		enable-method = "psci";
+		clocks = <&scmi_dvfs 2>;
+	};
+};
+
+&soc {
+	i2c0: i2c@28011000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28011000 0x0 0x1000>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "smbus_alert";
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@28012000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28012000 0x0 0x1000>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "smbus_alert";
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@28013000 {
+		compatible = "phytium,i2c";
+		reg = <0x0 0x28013000 0x0 0x1000>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	onewire0: onewire@2803f000 {
+		compatible = "phytium,w1";
+		reg = <0x0 0x2803f000 0x0 0x1000>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	i3c0: i3c-master@28045000 {
+		compatible = "phytium,cdns-i3c-master";
+		reg = <0x0 0x28045000 0x0 0x1000>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_100mhz>, <&sysclk_100mhz>;
+		clock-names = "pclk", "sysclk";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-scl-hz = <400000>;
+		i3c-scl-hz = <1000000>;
+		status = "disabled";
+	};
+
+	i3c1: i3c-master@28046000 {
+		compatible = "phytium,cdns-i3c-master";
+		reg = <0x0 0x28046000 0x0 0x1000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_100mhz>, <&sysclk_100mhz>;
+		clock-names = "pclk", "sysclk";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-scl-hz = <400000>;
+		i3c-scl-hz = <1000000>;
+		status = "disabled";
+	};
+
+	i3c2: i3c-master@28047000 {
+		compatible = "phytium,cdns-i3c-master";
+		reg = <0x0 0x28047000 0x0 0x1000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_100mhz>, <&sysclk_100mhz>;
+		clock-names = "pclk", "sysclk";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-scl-hz = <400000>;
+		i3c-scl-hz = <1000000>;
+		status = "disabled";
+	};
+
+	i3c3: i3c-master@28048000 {
+		compatible = "phytium,cdns-i3c-master";
+		reg = <0x0 0x28048000 0x0 0x1000>;
+		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_100mhz>, <&sysclk_100mhz>;
+		clock-names = "pclk", "sysclk";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-scl-hz = <400000>;
+		i3c-scl-hz = <1000000>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@2804e000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804e000 0x0 0x1000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm5: pwm@2804f000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x2804f000 0x0 0x1000>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm6: pwm@28050000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x28050000 0x0 0x1000>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	pwm7: pwm@28051000 {
+		compatible = "phytium,pwm";
+		reg = <0x0 0x28051000 0x0 0x1000>;
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+	};
+
+	adc0: adc@2807b000 {
+		compatible = "phytium,adc";
+		reg = <0x0 0x2807b000 0x0 0x1000>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {
+			reg = <0>;
+		};
+		channel@1 {
+			reg = <1>;
+		};
+		channel@2 {
+			reg = <2>;
+		};
+		channel@3 {
+			reg = <3>;
+		};
+		channel@4 {
+			reg = <4>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+	};
+
+	adc1: adc@2807c000 {
+		compatible = "phytium,adc";
+		reg = <0x0 0x2807c000 0x0 0x1000>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@0 {
+			reg = <0>;
+		};
+		channel@1 {
+			reg = <1>;
+		};
+		channel@2 {
+			reg = <2>;
+		};
+		channel@3 {
+			reg = <3>;
+		};
+		channel@4 {
+			reg = <4>;
+		};
+		channel@5 {
+			reg = <5>;
+		};
+		channel@6 {
+			reg = <6>;
+		};
+		channel@7 {
+			reg = <7>;
+		};
+	};
+
+	sgpio: sgpio@2807d000 {
+		compatible = "phytium,sgpio";
+		reg = <0x0 0x2807d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&sysclk_50mhz>;
+		ngpios = <96>;
+		bus-frequency = <48000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	macb0: ethernet@32010000 {
+		compatible = "cdns,phytium-gem";
+		reg = <0x0 0x32010000 0x0 0x2000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	macb1: ethernet@32012000 {
+		compatible = "cdns,phytium-gem";
+		reg = <0x0 0x32012000 0x0 0x2000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
+		clocks = <&sysclk_250mhz>, <&sysclk_48mhz>, <&sysclk_48mhz>, <&sysclk_250mhz>;
+		magic-packet;
+		status = "disabled";
+	};
+
+	jpeg0: jpeg@32b32000 {
+		compatible = "phytium,jpeg";
+		reg = <0x0 0x32b32000 0 0x1000>,
+		      <0x0 0x28072000 0 0x30>,
+		      <0x0 0x28073000 0 0x30>;
+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		phytium,ocm-buf-addr = <0x30c40000 0x30c60000>;
+		status = "disabled";
+	};
+};