LLM analysis and combined Kicad > Netlist > SKIDL > LLM analysis logic #247
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…kend complains about lack of an API key. refactor: Removed some unused hierarchy information from Circuit object and cleaned up get_circuit_info().
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Hi, Shane. I'll try to go through this as time permits. Hope to have some ideas by tonight. Lots of stuff here! Thanks for all the comments! |
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Some messages were appearing twice because the SKiDL logger objects were propagating their messages up to the simple logger you were using. I turned off propagation for the SKiDL loggers so now the messages appear only once. |
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@shanemmattner , it looks like you're analyzing all the SKiDL code, extracting subcircuits, placing all the subcircuit code into a file, adding wires to the subcircuit I/O, and finally executing the whole thing. What advantage does this give compared to just executing the original SKiDL code? One concern I have (which may be because I've misunderstood what's going on) is that the |
The
That's a good catch on the non-Net arguments. I designed So maybe the script I wrote is only useful for converting existing Kicad designs to SKIDL and analyzing the subcircuits. |
So you're re-building the SKiDL code so you can execute it within |
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I think we can do what I suggested as follows. Suppose we have a SKiDL file called from skidl import *
# Create a new circuit.
r = Part('Device', 'R', value='1K')
c = Part('Device', 'C', value='1u')
r & cThen we have another file called # This will run my_circuit.py and the circuit will be in the default_circuit object.
from my_circuit import *
# Now take the default_circuit object and do whatever: generate_netlist, analyze_circuit, etc.
default_circuit.generate_netlist()Then just run I think we can use this same technique in |
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I looked deeper into your code and saw that you already do something like what I suggested (around line 320), only you import the |
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Thanks for your thorough review. I'll try to refactor the code to use the existing SKIDL circuit since that would be more robust. I got busy today but I'll try to get this done tomorrow or over the weekend. |
…lt_circuit instead of re-assembling the skidl circuit one by one
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No rush! Nobody is holding a stopwatch on us.. A couple of random thoughts:
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…L_DIR environment variable
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Ok, I made a bunch of changes:
Here's an example of running the script now: |
This PR includes:
Here's a sample command where I point the script towards a sample project which has a part from a custom library. I have the script generate a netlist, then generate SKIDL files, then analyze each subcircuit with LLM calls
@devbisme the
kicad_skidl_llm.pyscript has a lot of logic in it I wasn't sure how to integrate with the main SKIDL logic.And one other question I had for you is that it seems like debug statements are being printed twice. Any idea what I might be doing wrong with the logging logic?