Merge pull request #1349 from diffblue/power3-works

Verilog: make power3 test work

Author: tautschnig

regression/verilog/expressions/power3.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE broken-smt-backend
 power3.sv
 
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The result is wrong.

regression/verilog/expressions/power3.sv

@@ -1,9 +1,9 @@
 module main;
 
   // Any arithmetic with x or z returns x.
-  initial assert('bx ** 1 === 'x);
-  initial assert('bz ** 1 === 'x);
-  initial assert(1 ** 'bx === 'x);
-  initial assert(1 ** 'bz === 'x);
+  initial assert('bx ** 1 === 32'hxxxx_xxxx);
+  initial assert('bz ** 1 === 32'hxxxx_xxxx);
+  initial assert(1 ** 'bx === 32'hxxxx_xxxx);
+  initial assert(1 ** 'bz === 32'hxxxx_xxxx);
 
 endmodule