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Pull requests: diffblue/hw-cbmc

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Pull requests list

SMV: test for LTL property with 'or' SMV Tests
#1203 opened Jul 14, 2025 by kroening Loading…
BMC: reconsider encoding of F
#1202 opened Jul 13, 2025 by kroening • Draft
BMC now checks for use of lasso symbol engines
#1201 opened Jul 13, 2025 by kroening Loading…
liveness-to-safety: exit if there is no supported property engines
#1200 opened Jul 13, 2025 by kroening Loading…
extend .gitignore
#1199 opened Jul 13, 2025 by kroening Loading…
BMC: exit early if there is no supported property engines
#1198 opened Jul 12, 2025 by kroening Loading…
Verilog: test for hierarchical identifier inside an assertion Tests Verilog
#1197 opened Jul 12, 2025 by kroening Loading…
SMV: variable definitions are now parse tree items cleanup SMV
#1196 opened Jul 12, 2025 by kroening Loading…
SMV: union operator SMV
#1186 opened Jul 7, 2025 by kroening • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening • Draft
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
1
introduce SMV enumeration type SMV
#1154 opened Jun 12, 2025 by kroening • Draft
Verilog: $isunknown Verilog
#1149 opened Jun 9, 2025 by kroening Loading…
1
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
BMC: completeness thresholds larger than one engines
#1115 opened May 18, 2025 by kroening Loading…
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
introduce verilog_sva_property_typet Verilog
#1081 opened Apr 23, 2025 by kroening Loading…
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: --initial-zero Verilog
#1001 opened Feb 20, 2025 by kroening Loading…
6
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
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