Merge pull request #1281 from diffblue/shift-works

Verilog: test verilog/asic-world-operators/shift.desc works

Author: tautschnig

regression/verilog/asic-world-operators/shift.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 shift.sv
 --module main --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The test shift_p7 fails.