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2 parents d4de8c0 + 1e9ef1b commit 9dc994aCopy full SHA for 9dc994a
regression/ebmc-spot/sva-buechi/s_eventually2.bmc.desc
@@ -1,4 +1,4 @@
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-KNOWNBUG
+CORE
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../../verilog/SVA/s_eventually2.sv
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--buechi --module main --bound 20
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^\[main\.p0\] always s_eventually main.reset \|\| main\.counter == 10: PROVED up to bound 20$
@@ -8,4 +8,3 @@ KNOWNBUG
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--
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^warning: ignoring
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-This gives the wrong answer for main.p0.
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